Method for integrated circuit mask patterning

Patent metadata

Field	Value
Publication number	US-9256709-B2
Application number	US-201414180233-A
Country	US
Kind code	B2
Filing date	Feb 13, 2014
Priority date	Feb 13, 2014
Publication date	Feb 9, 2016
Grant date	Feb 9, 2016

Abstract

Provided is a method of transforming an integrated circuit (IC) pattern into one or more patterns suitable for subsequent processing, such as mask fabrication. The method includes receiving an IC pattern that has an arbitrary shape, and using a computer, deriving an approximation IC pattern, wherein the approximation IC pattern is in a shape that is a user-defined fabrication-friendly shape, such as a rectangle or an ellipse. The method further includes calculating a pattern approximation error between the IC pattern and the approximation IC pattern. The method further includes checking whether the pattern approximation error is less than a user-defined threshold. If it is, the method further includes outputting the approximation IC pattern for subsequent fabrication. Otherwise, the method further includes splitting the IC pattern into a plurality of subparts, and recursively transforming each of the plurality of subparts.

First claim

What is claimed is:

1. A method of transforming a first integrated circuit (IC) pattern, wherein the first IC pattern includes a shape that is not one of a plurality of user-defined shapes, the method comprising the steps of:
using a computer, deriving a second IC pattern approximating the first IC pattern, wherein the second IC pattern includes a shape that is one of the plurality of user-defined shapes;
calculating a pattern approximation error between the first IC pattern and the second IC pattern; and
upon a condition in which the pattern approximation error is greater than a user-defined threshold, performing the steps of:
splitting the first IC pattern into a plurality of sub-patterns; and
recursively transforming each of the plurality of sub-patterns.

2. The method of claim 1 , wherein the first IC pattern includes a plurality of sub-patterns and a plurality of second IC sub-patterns have been derived respectively for the plurality of sub-patterns, further comprising:
connecting the plurality of second IC sub-patterns.

3. The method of claim 1 , further comprising, when the pattern approximation error is equal to or less than the user-defined threshold:
outputting the second IC pattern in a computer-readable format.

4. The method of claim 1 , wherein the plurality of user-defined shapes includes a rectangle.

5. The method of claim 1 , wherein the plurality of user-defined shapes includes an ellipse.

6. The method of claim 1 , wherein the second IC pattern has about the same area as the first IC pattern.

7. The method of claim 1 , wherein the calculating the pattern approximation error includes:
determining a center of mass of the first IC pattern; and
upon a condition in which the center of mass is outside of the first IC pattern, assigning a value to the pattern approximation error, wherein the value is greater than the user-defined threshold.

8. The method of claim 1 , further comprising:
using a computer, determining a center of mass of the first IC pattern; and
upon a condition in which the center of mass is outside of the first IC pattern, performing the steps of:
separating the first IC pattern into a plurality of first IC pattern subsets before the deriving the second IC pattern,
wherein the steps of calculating, deriving, and performing are performed on each of the first IC pattern subsets.

9. The method of claim 1 , wherein the deriving the second IC pattern includes:
mapping the first IC pattern to a number (N) of pixels, wherein each of the N pixels has an x-coordinate and an y-coordinate, and is represented by (x i , y i ) where i∈[1,N];
calculating an area, a, of the first IC pattern;
calculating a geometric center (x w ,y w ) of the N pixels, wherein

x
w

=

1
N

⁢

∑
1
N

⁢

⁢

x
i

;

and

y
w

=

1
N

⁢

∑
1
N

⁢

⁢

y
i

;

constructing a relative position matrix, M, wherein M is a N by 2 (N×2) array of real numbers and i∈[1,N]:

M
=

[

x
1

-

x
w

,

y
1

-

y
w

⋮

x
i

-

x
w

,

y
i

-

y
w

⋮

x
N

-

x
w

,

y
N

-

y
w

]

∈

ℜ

N
×
2

constructing a covariance matrix, A, A=M T M;
calculating eigenvectors u=

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Yu Jue-Chin
• Hsieh Lun
• Chen Pi-Tsung
• Chou Shuo-Yen
• Liu Ru-Gun

Classifications

• G03F1/70

  Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging · CPC title

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G03F1/36 Primary

  Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes · CPC title

• G06F30/39

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• G06F17/5081 Primary

  Physics · mapped topic