On-chip frequency monitoring

Patent metadata

Field	Value
Publication number	US-10514401-B2
Application number	US-201715667116-A
Country	US
Kind code	B2
Filing date	Aug 2, 2017
Priority date	Aug 2, 2017
Publication date	Dec 24, 2019
Grant date	Dec 24, 2019

Abstract

In certain aspects of the disclosure, a frequency monitor includes a counter configured to receive a monitored clock signal, to count a number of periods of the monitored clock signal over a predetermined time duration, and to output a count value corresponding to the number of periods of the monitored clock signal. The frequency monitor also includes a comparator configured to receive the count value from the counter, to receive an expected count value, to compare the count value from the counter with the expected count value, and to output a pass status signal or a fail status signal based on the comparison.

First claim

What is claimed is:

1. A frequency monitor, comprising:
a counter configured to receive a monitored clock signal, to count a number of periods of the monitored clock signal over a predetermined time duration, and to output a count value corresponding to the number of periods of the monitored clock signal; and
a comparator configured to receive the count value from the counter, to receive an expected count value, to mask out N least significant bits (LSBs) of the count value from the counter, to mask out N LSBs of the expected count value, to compare unmasked bits of the count value with unmasked bits of the expected count value, and to output a pass status signal or a fail status signal based on the comparison.

2. The frequency monitor of claim 1 , wherein the comparator is configured to output the pass status signal if the unmasked bits of the count value from the counter match the unmasked bits of the expected count value.

3. The frequency monitor of claim 2 , wherein the comparator is configured to output the fail status signal if the unmasked bits of the count value from the counter do not match the unmasked bits of the expected count value.

4. The frequency monitor of claim 1 , wherein N is specified by a mask control signal input to the comparator.

5. The frequency monitor of claim 1 , wherein:
in a self-test mode, the counter is configured to receive a test clock signal, to count a number of periods of the test clock signal over a test time duration, and to output a test count value corresponding to the number of periods of the test clock signal; and
in the self-test mode, the comparator is configured to receive the test count value from the counter, to compare the test count value with an expected test count value, and to output a self-test status signal indicating whether the frequency monitor is functioning properly based on the comparison of the test count value with the expected test count value.

6. The frequency monitor of claim 5 , wherein the frequency monitor further comprises a multiplexer having a first input coupled to the test clock signal, a second input coupled to the monitored clock signal, and an output coupled to the counter, wherein the multiplexer is configured to couple the test clock signal to the counter in the self-test mode, and to couple the monitored clock signal to the counter in a non-self-test mode.

7. The frequency monitor of claim 5 , wherein the self-test status signal indicates the frequency monitor is functioning properly if the test count value is within a predetermined range of the expected test count value, and the self-test status signal indicates the frequency monitor is not functioning properly if the test count value is outside the range of the expected test count value.

8. The frequency monitor of claim 1 , wherein the monitored clock signal is a clock signal input to a processor located on a same chip as the frequency monitor.

9. A frequency monitor, comprising:
a count control device configured to output a count enable signal;
a synchronizer configured to synchronize the count enable signal with a monitored clock signal to generate a synchronized count enable signal;
a counter configured to receive the synchronized count enable signal and the monitored clock signal, to count a number of periods of the monitored clock signal in response to the synchronized count enable signal, and to output a count value corresponding to the number of periods of the monitored clock signal; and
a comparator configured to receive the count value from the counter, to receive an expected count value, to compare the count value from the counter with the expected count value, and to output a pass status signal or a fail status signal based on the comparison.

10. The frequency monitor of claim 9 , wherein the synchronizer is configured to synchronize the count enable signal with the monitored clock signal by aligning an edge of the count enable signal with an edge of the monitored clock signal.

11. The frequency monitor of claim 9 , wherein the count control device is configured to receive a reference clock signal, and to output the count enable signal for a predetermined number of periods of the reference clock signal.

12. The frequency monitor of claim 9 , wherein the synchronizer comprises a latch having a signal input configured to receive the count enable signal, a clock input configured to receive the monitored clock signal, and an output configured to output the synchronized count enable signal, wherein the latch is configured to latch a logic value of the count enable signal on an edge of the monitored clock signal, and to output the latched logic value at the output of the latch.

13. A method for frequency monitoring, comprising:
receiving a monitored clock signal;
counting a number of periods of the monitored clock signal over a predetermined time duration;
generating a count value corresponding to the number of periods of the monitored clock signal counted over the predetermined time duration;
masking out N least significant bits (LSBs) of the generated count value;
masking out N LSBs of the expected count value;
comparing unmasked bits of the generated count value with unmasked bits of the expected count value; and
generating a pass status signal or a fail status signal based on the comparison.

14. The method of claim 13 , wherein generating the pass status signal or the fail status signal comprises:
generating the pass status signal if the unmasked bits of the generated count value match the unmasked bits of the expected count value; and
generating the fails status signal if the unmasked bits of the generated count value do not match the unmasked bits of the expected count value.

15. The method of claim 13 , further comprises:
synchronizing a count enable signal with the monitored clock signal to generate a synchronized count enable signal;
wherein counting the number of periods of the monitored clock signal over the predetermined time duration comprises starting the counting on an edge of the synchronized count enable signal.

16. The method of claim 15 , wherein synchronizing the count enable signal with the monitored clock signal comprises aligning an edge of the count enable signal with an edge of the monitored clock signal.

17. A frequency monitoring system, comprising:
a multiplexer having multiple inputs and an output, wherein each of the multiple inputs is coupled to a respective one of multiple clock signals;
a select controller configured to instruct the multiplexer to sequentially couple each clock signal in a subset of the multiple clock signals to the output of the multiplexer;
a frequency monitor coupled to the output of the multiplexer, wherein the frequency monitor is configured to sequentially receive each clock signal in the subset of the multiple clock signals, and wherein, for each clock signal in the subset of the multiple clock signals, the frequency monitor is configured to determine whether the clock signal is within a respective frequency range, and to output a status signal based on the determination; and
a register that stores a set of monitor indicators, wherein each of the monitor indicators corresponds to a respective one of the multiple clock signals, and a value of each of the monitor indicators indicates whether the respective one of the multiple clock signals is in the subset of the multiple clock signals.

18. The frequency monitoring system of claim 17 , wherein the value of each of the monitor indicators is a bit value.

19. The frequency moni

Assignees

• Qualcomm Inc

Inventors

• Duggal Bipin
• Gulati Rahul
• DENA Sina

Classifications

• G01R29/033

  giving an indication of the number of times this occurs {, i.e. multi-channel analysers (the characteristic being frequency)} · CPC title

• G01R31/3187 Primary

  Built-in tests · CPC title

• G01R23/02 Primary

  Arrangements for measuring frequency, e.g. pulse repetition rate; Arrangements for measuring period of current or voltage · CPC title

• G01R31/31727

  Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks (G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922) · CPC title

• G01R23/10

  by converting frequency into a train of pulses, which are then counted {, i.e. converting the signal into a square wave} · CPC title