Hybrid on-chip clock controller techniques for facilitating at-speed scan testing and scan architecture support

Patent metadata

Field	Value
Publication number	US-9500706-B2
Application number	US-201414161348-A
Country	US
Kind code	B2
Filing date	Jan 22, 2014
Priority date	Jan 22, 2014
Publication date	Nov 22, 2016
Grant date	Nov 22, 2016

Abstract

Various aspects described or referenced herein are directed to different methods, systems, and computer program products for implementing hybrid on-chip clock controller techniques for facilitating at-speed scan testing and scan architecture support.

First claim

It is claimed:

1. A method, comprising:
receiving, at a semiconductor device to be tested, an external test clock signal, wherein the external test clock signal includes a first set of external test clock pulses;
determining, using the external test clock signal, a first pulse count value representing the first set of external test clock pulses;
causing the semiconductor device to generate a first set of higher frequency test clock signals for a first configurable number of clock cycles during a first capture period, wherein the first configurable number of clock cycles corresponds to the first pulse count value;
generating at the semiconductor device an on-chip clock (OCC) Clock Chain signal, the OCC Clock Chain signal including a first set of OCC Clock Chain data represented by a first set of bits;
determining, using the OCC Clock Chain signal, an OCC pulse count value representing a specific number of higher frequency test clock signal(s) to be generated at the semiconductor device during a second capture period; and
causing the semiconductor device to generate a second set of higher frequency test clock signals for a second configurable number of clock cycles during the second capture period, wherein the second configurable number of clock cycles corresponds to the OCC pulse count value.

2. The method of claim 1 :
wherein the first pulse count value corresponds to a first number of higher frequency test clock periods to be generated at the semiconductor device during the first capture period; and
wherein the OCC pulse count value corresponds to a second number of higher frequency test clock periods to be generated at the semiconductor device during the second capture period.

3. The method of claim 1 :
wherein the OCC Clock Chain data is representative of a second number of higher frequency test clock periods to be generated at the semiconductor device during the second capture period.

4. The method of claim 1 further comprising:
generating a first count value that represents a first period of time during which a first number of periods of the external test clock signal are counted to determine a number of higher frequency test clock periods to be generated during the first capture period.

5. The method of claim 1 further comprising:
causing the semiconductor device to automatically and dynamically switch to a test clock pulse control mode of operation during a first time interval; and
causing the semiconductor device to automatically and dynamically switch to an OCC clock chain control mode of operation during a second time interval.

6. The method of claim 1 further comprising:
causing the semiconductor device to automatically and dynamically switch to a test clock pulse control mode of operation during a first time interval;
wherein, during the test clock pulse control mode of operation, a first plurality of operations are performed, including: the receiving of the external test clock signal, the determining of the first pulse count value; and the generating of the first set of higher frequency test clock signals;
causing the semiconductor device to automatically and dynamically switch to an OCC clock chain control mode of operation during a second time interval;
wherein, during the OCC clock chain control mode of operation, a second plurality of operations are performed including: the generating of the OCC Clock Chain signal, the determining of the OCC pulse count value; and the generating of the second set of higher frequency test clock signals.

7. The method of claim 1 further comprising:
programming, using a first ScanIn signal, a first set of scan flops located at the semiconductor device;
programming, using an OCC Clock Chain ScanIn signal, a second set of scan flops used to generate the OCC Clock Chain signal; and
wherein the first ScanIn signal is different from the OCC Clock Chain ScanIn signal.

8. The method of claim 1 further comprising:
concurrently receiving, at the semiconductor device, a first plurality of OCC Clock Chain ScanIn signals; and
generating, at the semiconductor device and using the first plurality of OCC Clock Chain ScanIn signals, an OCC Clock Chain signal stream which includes the OCC Clock Chain signal.

9. A semiconductor device, comprising:
a clock generator;
an external test clock input configured or designed to receive an external test clock signal, wherein the external test clock signal includes a first set of external test clock pulses;
an external test clock counter coupled to the external test clock input, the external test clock counter being configured or designed to determine, using the external test clock signal, a first pulse count value representing the first set of external test clock pulses;
an on-chip clock (OCC) Clock Chain engine configured or designed to generate an OCC Clock Chain signal, the OCC Clock Chain signal including a first set of OCC Clock Chain data represented by a first set of bits;
an OCC Clock Chain decoder configured or designed to determine, using the OCC Clock Chain signal, an OCC pulse count value representing a specific number of higher frequency test clock signal(s) to be generated at the semiconductor device during a second capture period;
a fast test mode pulse generating logic coupled to the clock generator, the fast test mode pulse generating logic being configured or designed to cause the clock generator to generate a first set of higher frequency test clock signals for a first configurable number of clock cycles during a first capture period, wherein the first configurable number of clock cycles corresponds to the first pulse count value; and
wherein the fast test mode pulse generating logic is further configured or designed to cause the clock generator to generate a second set of higher frequency test clock signals for a second configurable number of clock cycles during the second capture period, wherein the second configurable number of clock cycles corresponds to the OCC pulse count value.

10. The semiconductor device of claim 9 :
wherein the first pulse count value corresponds to a first number of higher frequency test clock periods to be generated at the semiconductor device during the first capture period; and
wherein the OCC pulse count value corresponds to a second number of higher frequency test clock periods to be generated at the semiconductor device during the second capture period.

11. The semiconductor device of claim 9 :
wherein the OCC Clock Chain data is representative of a second number of higher frequency test clock periods to be generated at the semiconductor device during the second capture period.

12. The semiconductor device of claim 9 further comprising:
a Twindow Counter configured or designed to generate a first count value that represents a first period of time during which a first number of periods of the external test clock signal are counted to determine a number of higher frequency test clock periods to be generated during the first capture period.

13. The semiconductor device of claim 9 further comprising:
a switch or MUX configured to receive a first signal for causing the semiconductor device to automatically and dynamically switch to a test clock pulse control mode of operation during a first time interval; and
wherein the switch or MUX is further configured or designed to receive a second signal for causing the semiconductor device to automatically and dynamically switch to an OCC clock chain control mode of operation during a second time interval.

14. The semiconductor device of claim 9 further comprising:
a switch or MUX configured to receive a first signal for

Assignees

• Nvidia Corp

Inventors

• Sanghani Amit
• Nataraj Sagar
• Natarajan Karthikeyan
• Yang Bo

Classifications

• G01R31/318594 Primary

  Timing aspects (clock circuits G01R31/318552) · CPC title

• G01R31/318522

  Test of Sequential circuits (test of microprocessors G06F11/2236, test of ALU's G06F11/2226) · CPC title

• G01R31/318552

  Clock circuits details · CPC title