Method for reduced power clock frequency monitoring

Patent metadata

Field	Value
Publication number	US-2016359476-A1
Application number	US-201514730473-A
Country	US
Kind code	A1
Filing date	Jun 4, 2015
Priority date	Jun 4, 2015
Publication date	Dec 8, 2016
Grant date	—

Abstract

An apparatus may include first and second clock monitors. The first clock monitor may be configured to receive a first clock signal and assert a first signal if the frequency of the first clock signal is greater than a first upper threshold and assert a second signal if the frequency of the first clock signal is less than a first lower threshold. The second clock monitor may be configured to receive a second clock signal with a frequency higher than that of the first clock signal. The second clock monitor may be configured to compare the second clock signal, dependent upon the first clock signal, to second upper and lower thresholds and assert a third signal if the frequency of the second clock signal is greater than the second upper threshold and assert a fourth signal if the frequency is less than the second lower threshold.

First claim

1 . An apparatus, comprising:
a first clock monitoring circuit configured to:
receive a first clock signal;
assert a first signal in response to a determination that the frequency of the first clock signal is greater than a first upper threshold value; and
assert a second signal in response to a determination that the frequency of the first clock signal is less than a first lower threshold value; and
a second clock monitoring circuit configured to:
receive a second clock signal, wherein a frequency of the second clock signal is higher than a frequency of the first clock signal;
compare, dependent upon the first clock signal, the frequency of the second clock signal to a second upper threshold value and a second lower threshold value;
assert a third signal if the frequency of the second clock signal is greater than the second upper threshold value; and
assert a fourth signal if the frequency of the second clock signal is less than the second lower threshold value;
wherein a power consumption of the second clock monitoring circuit is less than a power consumption of the first clock monitoring circuit.

2 . The apparatus of claim 1 , wherein to compare the frequency of the second clock signal to the second upper threshold value and the second lower threshold value, the second clock monitoring circuit is further configured to determine a number of rising transitions of the second clock signal occurring during a given duration of the first clock signal.

3 . The apparatus of claim 1 , wherein the second clock monitoring circuit is further configured to, in response to the assertion of the third signal or the fourth signal, store a value corresponding to a time when the assertion occurs.

4 . The apparatus of claim 1 , further comprising a third clock monitoring circuit configured to:
receive a third clock signal, wherein a frequency of the third clock signal is higher than the frequency of the first clock signal; compare, dependent upon the first clock signal, the frequency of the third clock signal to a third upper threshold value and a third lower threshold value; assert a fifth signal if the frequency of the third clock signal is greater than the third upper threshold value; and assert a sixth signal if the frequency of the third clock signal is less than the third lower threshold value.

5 . The apparatus of claim 1 , wherein the frequency of the second clock signal is dependent upon the frequency of the first clock signal.

6 . The apparatus of claim 1 , wherein the frequency of the second clock signal is selectable, and wherein the second upper threshold value and second lower threshold value are determined dependent upon the selected frequency of the second clock signal.

7 . The apparatus of claim 1 , wherein the second upper threshold value and second lower threshold value are independently selectable.

8 . A method, comprising:
receiving a first clock signal; asserting a first signal in response to a determination that the frequency of the first clock signal is greater than a first upper threshold value; asserting a second signal in response to a determination that the frequency of the first clock signal is less than a first lower threshold value; receiving a second clock signal, wherein a frequency of the second clock signal is higher than a frequency of the first clock signal; comparing, dependent upon the first clock signal, the frequency of the second clock signal to a second upper threshold value and a second lower threshold value; asserting a third signal if the frequency of the second clock signal is greater than the second upper threshold value; and asserting a fourth signal if the frequency of the second clock signal is less than the second lower threshold value; wherein the frequency of the second clock signal is dependent upon the frequency of the first clock signal.

9 . The method of claim 8 , wherein comparing the frequency of the second clock signal to the second upper threshold value and the second lower threshold value, further comprises determining a number of rising transitions of the second clock signal occurring during a given duration of the first clock signal.

10 . The method of claim 8 , further comprising:
receiving a third clock signal, wherein a frequency of the third clock signal is higher than the frequency of the first clock signal; comparing, dependent upon the first clock signal, the frequency of the third clock signal to a third upper threshold value and a third lower threshold value; asserting a fifth signal if the frequency of the third clock signal is greater than the third upper threshold value; and asserting a sixth signal if the frequency of the third clock signal is less than the third lower threshold value.

11 . The method of claim 8 , further comprising, in response to asserting the third signal or the fourth signal, storing a value corresponding to a time when the third signal or the fourth signal is asserted.

12 . The method of claim 8 , wherein the frequency of the second clock signal is selectable and wherein the second upper threshold value and second lower threshold value are determined dependent upon the selected frequency of the second clock signal.

13 . The method of claim 8 , wherein the second upper threshold value and second lower threshold value are independently selectable.

14 . The method of claim 8 , further comprising generating a reset signal in response to an assertion of the third signal or an assertion of the fourth signal.

15 . A system comprising:
a first clock source configured to generate a first clock signal; a second clock source configured to generate a second clock signal, wherein a frequency of the second clock signal is higher than a frequency of the first clock signal; and a clock monitoring unit configured to:
receive the first clock signal;
assert a first signal in response to a determination that the frequency of the first clock signal is greater than a first upper threshold value;
assert a second signal in response to a determination that the frequency of the first clock signal is less than a first lower threshold value;
receive a second clock signal;
compare, dependent upon the first clock signal, the frequency of the second clock signal to a second upper threshold value and a second lower threshold value;
assert a third signal if the frequency of the second clock signal is greater than the second upper threshold value; and
assert a fourth signal if the frequency of the second clock signal is less than the second lower threshold value;
wherein the frequency of the second clock signal is dependent upon the frequency of the first clock signal.

16 . The system of claim 15 , wherein to compare the frequency of the second clock signal to the second upper threshold value and the second lower threshold value, the clock monitoring unit is further configured to determine a number of rising transitions of the second clock signal occurring during a given duration of the first clock signal.

17 . The system of claim 15 , wherein the clock monitoring unit is further configured to:
receive a third clock signal, wherein a frequency of the third clock signal is higher than the frequency of the first clock signal; compare, dependent upon the first clock signal, the frequency of the third clock signal to a third upper threshold value and a third lower threshold value; assert a fifth signal if the frequency of the third clock signal is greater than the third upper threshold value; and assert a sixth signal if the frequency of the third clock signa

Assignees

• Apple Inc

Inventors

• Yu Shu-Yi
• Allegrucci Jean-Didier
• Paaske Timothy
• Balkan Deniz

Classifications

• H03K5/26

  the characteristic being duration, interval, position, frequency, or sequence · CPC title

• H03K5/19 Primary

  Monitoring patterns of pulse trains (indicating amplitude G01R19/00; indicating frequency G01R23/00; measuring characteristics of individual pulses G01R29/02) · CPC title