Monitoring on-chip clock control during integrated circuit testing

Patent metadata

Field	Value
Publication number	US-9234938-B2
Application number	US-201414270964-A
Country	US
Kind code	B2
Filing date	May 6, 2014
Priority date	May 6, 2014
Publication date	Jan 12, 2016
Grant date	Jan 12, 2016

Abstract

The On-Chip Clock (OCC) circuit is for testing an integrated circuit having logic blocks connected in scan chains. An OCC controller is configured to receive a plurality of clock signals and output a plurality of shift/capture clock signals for use by the scan chains of logic blocks, the plurality of shift/capture clock signals including at least two consecutive at-speed capture clock pulses. An OCC monitor is configured to provide a verification of OCC operation based upon the at least two consecutive at-speed capture clock pulses. The OCC monitor may include a plurality of registers configured to provide delayed pulses based upon the at least two consecutive at-speed capture clock pulses, a counter configured to count differences between the delayed pulses, and an output register coupled to the counter and configured to provide a static data verification (e.g. output on an integrated circuit pad) for the test engineer.

First claim

That which is claimed is:

1. An On-Chip Clock (OCC) circuit of an integrated circuit having logic blocks coupled in scan chains, the OCC circuit comprising:
a clock generator configured to generate a plurality of clock signals;
an OCC controller configured to receive the plurality of clock signals and output a plurality of shift/capture clock signals for use by the scan chains of logic blocks, the plurality of shift/capture clock signals comprising at least two consecutive at-speed capture clock pulses; and
an OCC monitor configured to provide a verification of OCC operation based upon the at least two consecutive at-speed capture clock pulses.

2. The OCC circuit according to claim 1 , wherein the OCC monitor comprises a plurality of registers configured to provide delayed pulses based upon the at least two consecutive at-speed capture clock pulses.

3. The OCC circuit according to claim 2 , wherein the OCC monitor further comprises a counter configured to count differences between the delayed pulses.

4. The OCC circuit according to claim 3 , wherein the OCC monitor further comprises an output register coupled to the counter and configured to provide a static data verification output on an integrated circuit pad.

5. The OCC circuit according to claim 1 , wherein the clock generator comprises a phased locked loop (PLL).

6. The OCC circuit according to claim 5 , wherein the clock generator further comprises a clock shaper, clock divider and clock multiplier coupled to the PLL.

7. The OCC circuit according to claim 1 , wherein the clock generator varies the plurality of clock signals by at least one of frequency, waveform shape, phase and pulse duration.

8. The OCC circuit according to claim 1 , wherein the OCC controller comprises a programmable clock multiplexer (MUX).

9. In integrated circuit comprising:
a plurality of input/output pads;
circuit logic blocks coupled in scan chains; and
an On-Chip Clock (OCC) circuit comprising
a phased locked loop (PLL) clock generator configured to generate a plurality of clock signals,
an OCC controller configured to receive the plurality of clock signals and output a plurality of shift/capture clock signals for use by the scan chains of logic blocks, the plurality of shift/capture clock signals comprising at least two consecutive at-speed capture clock pulses, and
an OCC monitor configured to provide a verification of OCC operation based upon the at least two consecutive at-speed capture clock pulses.

10. The integrated circuit according to claim 9 , wherein the PLL clock generator comprises a PLL and a clock shaper, clock divider and clock multiplier coupled to the PLL.

11. The integrated circuit according to claim 9 , wherein the PLL clock generator varies the plurality of clock signals by at least one of frequency, waveform shape, phase and pulse duration.

12. The integrated circuit according to claim 9 , wherein the OCC controller comprises a programmable clock multiplexer (MUX); and further comprising a clock chain controller configured to provide instructions to the programmable clock MUX regarding the number of shift/capture clock signals needed.

13. The integrated circuit according to claim 9 , wherein the OCC monitor comprises:
a plurality of registers configured to provide delayed pulses based upon the at least two consecutive at-speed capture clock pulses;
a counter configured to count differences between the delayed pulses; and
an output register coupled to the counter and configured to provide a static data verification output to at least one input/output pad.

14. A method of providing an On-Chip Clock (OCC) in an integrated circuit having logic blocks coupled in scan chains, the method comprising:
generating a plurality of clock signals with a clock generator;
receiving the plurality of clock signals at an OCC controller and outputting a plurality of shift/capture clock signals for use by the scan chains of logic blocks, the plurality of shift/capture clock signals comprising at least two consecutive at-speed capture clock pulses; and
monitoring the at least two consecutive at-speed capture clock pulses with an OCC monitor to provide a verification of OCC operation.

15. The method according to claim 14 , wherein the clock generator comprises a phased locked loop (PLL).

16. The method according to claim 15 , wherein the clock generator further comprises a clock shaper, clock divider and clock multiplier coupled to the PLL.

17. The method according to claim 14 , wherein generating the plurality of clock signals with the clock generator includes varying the plurality of clock signals by at least one of frequency, waveform shape, phase and pulse duration.

18. The method according to claim 14 , wherein the OCC controller comprises a programmable clock multiplexer (MUX).

19. The method according to claim 14 , wherein monitoring comprises providing delayed pulses based upon the at least two consecutive at-speed capture clock pulses being monitored.

20. The method according to claim 19 , wherein monitoring further comprises counting differences between the delayed pulses.

21. The OCC circuit according to claim 20 , wherein monitoring further comprises providing a static data verification output on an input/output pad of the integrated circuit based upon the counting.

Assignees

• St Microelectronics Int Nv

Inventors

• Khullar Shray
• Bahl Swapnil

Classifications

• G01R31/318552 Primary

  Clock circuits details · CPC title

• G01R31/31705

  Debugging aspects, e.g. using test circuits for debugging, using dedicated debugging test circuits (generation of test sequences therefor G01R31/31835, using scan test therefor G01R31/318544) · CPC title

• G01R31/31727 Primary

  Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks (G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922) · CPC title

• G01R31/2815

  Functional tests, e.g. boundary scans, using the normal I/O contacts (contacting devices G01R31/2808; testing digital circuits G01R31/317, G06F11/00) · CPC title

• G01R31/31704

  Design for test; Design verification (concerning scan tests G01R31/318583; computer-aided design G06F30/00) · CPC title