Histogram based error estimation and correction

Patent metadata

Field	Value
Publication number	US-9748966-B2
Application number	US-201615231415-A
Country	US
Kind code	B2
Filing date	Aug 8, 2016
Priority date	Aug 6, 2015
Publication date	Aug 29, 2017
Grant date	Aug 29, 2017

Abstract

A system includes an analog-to-digital converter (ADC) including an ADC input terminal; an ADC output terminal; and analog components configured to convert an analog signal received at the ADC input terminal to a digital signal. The system also includes a histogram estimation circuit coupled to the ADC output terminal and configured to generate information on a plurality of codes generated by the ADC and determine a region defining a range of codes corresponding to an occurrence of an error caused by the analog components of the ADC. The system also includes a dither circuit coupled to the ADC input terminal and configured to introduce a dither in the analog signal to generate a modified analog signal.

First claim

What is claimed is:

1. A system comprising:
an analog-to-digital converter (ADC) comprising:
an ADC input terminal,
an ADC output terminal, and
analog components configured to convert an analog signal received at the ADC input terminal to a digital signal;

a dither circuit coupled to the ADC input terminal and configured to introduce a dither in the analog signal to generate a modified analog signal; and
a histogram estimation circuit coupled to an output of the ADC and configured to determine a direction of error correction based on information provided by the introduction of the dither in the analog signal and information of a plurality of codes output by the ADC in a target region.

2. The system of claim 1 , wherein the histogram estimation circuit is further configured to:
receive a first and second signal in digital format from the ADC, the first and second signal in digital format correspond to a respective first and second analog signal received at the ADC input terminal, wherein a first and second dither is being added to the first and second analog signal respectively;
calculate a first histogram of digital values corresponding to the first signal without the first dither;
calculate a second histogram of digital values corresponding to the second signal without the second dither;
compare the first and second histograms at the target region corresponding to an occurrence of an error caused by the analog components of the ADC; and
determine an error correction based on the comparison of the first and second histogram.

3. The system of claim 2 ,
wherein a portion of the first histogram represents a target histogram,
wherein a portion of the second histogram represents an actual histogram, and
wherein the histogram estimation circuit configured to determine the error correction comprises the histogram estimation circuit configured to apply a correction to an analog component of the analog components such that a difference between the target histogram and the actual histogram is reduced.

4. The system of claim 1 ,
wherein the dither circuit is further configured to introduce a positive dither to the analog signal to generate a positive modified analog signal;
wherein the ADC is configured to convert the positive modified analog signal to a positive modified digital signal; and
wherein the histogram estimation circuit is configured to subtract the positive dither from the positive modified digital signal and generate a first histogram of a plurality of codes generated by the ADC corresponding to the positive modified digital signal without the positive dither.

5. The system of claim 4 ,
wherein the dither circuit is further configured to introduce a negative dither to the analog signal to generate a negative modified analog signal;
wherein the ADC is configured to convert the negative modified analog signal to a negative modified digital signal; and
wherein the histogram estimation circuit is configured to subtract the negative dither from the negative modified digital signal and generate a second histogram of a plurality of codes generated by the ADC corresponding to the negative modified digital signal without the negative dither.

6. The system of claim 5 , wherein the target region corresponds to a first range of codes of the first histogram, wherein the histogram estimation circuit is further configured to:
compare a plurality of codes between the first histogram and the second histogram at the first range of codes; and
determine the direction of error correction based on the comparison.

7. The system of claim 5 , wherein the target region corresponds to a first range of codes of the first histogram and a second range of codes of the second histogram, wherein the histogram estimation circuit is further configured to:
compare a plurality of codes between the first histogram and the second histogram within the first range of codes to determine an error correction based on the first comparison; and
compare a plurality of codes between the first histogram and the second histogram within the second range of codes to determine an error correction based on the second comparison.

8. The system of claim 7 , wherein the histogram estimation circuit is further configured to reduce a convergence time for error correction by determining an error correction based on the first comparison and an error correction based on the second comparison.

9. The system of claim 1 , wherein the ADC comprises a pipeline ADC comprising at least two stages, one of the at least two stages comprising:
a flash ADC comprising a flash ADC input terminal and a flash ADC output terminal, the flash ADC input terminal configured to receive the analog signal;
a digital to analog converter (DAC) comprising a DAC input, the DAC input coupled to the ADC output terminal; and
a subtractor configured to subtract an output signal of the DAC from the analog signal to generate a residue signal.

10. A system comprising:
a pipeline analog-to-digital converter (ADC) comprising at least two stages, one of the at least two stages comprising:
a flash ADC comprising an input configured to receive an analog signal,
a digital-to-analog converter (DAC), comprising a DAC input configured to receive a digital signal from the flash ADC, and
a gain amplifier configured to amplify a difference between an output signal from the DAC and the analog signal;

a dither circuit coupled to the input of the pipeline ADC and configured to introduce a dither in the analog signal to generate a modified analog signal; and
an estimation circuit coupled to an output of the pipeline ADC and configured to determine a direction of error correction based on information provided by the introduction of the dither in the analog signal and information of a plurality of codes output by the pipeline ADC in a target region.

11. The system of claim 10 , wherein the estimation circuit is further configured to determine the direction of error correction through a background calibration without interruption of an operation of the pipeline ADC.

12. The system of claim 10 , wherein the estimation circuit comprises a hardware processor, the hardware processor configured to:
receive a first signal from the pipeline ADC, the first signal comprising a digital signal corresponding to the modified analog signal comprising a first dither;
receive a second signal from the pipeline ADC, the second signal comprising a second digital signal corresponding to a second modified analog signal comprising a second dither;
determine a range of codes comprising a region corresponding to a transition region of the flash ADC;
calculate a first histogram of pipeline ADC output signal values corresponding to the first signal without the first dither;
calculate a second histogram of pipeline ADC output signal values corresponding to the second signal without the second dither;
compare the first histogram and second histogram at the region corresponding to a transition region of the flash ADC; and
determine the direction of error correction based on the comparison of the first histogram and second histogram.

13. The system of claim 12 , wherein the hardware processor is further configured to determine the direction of error correction through a determination of a direction that reduces a difference between the first histogram and the second histogram.

14. The system of claim 10 ,
wherein the dither circuit is further configured to introduce a positive dither in the analog signal to generate the modified analog signal;
wherein the pipeline ADC is configured to convert the modified analog si

Assignees

• Texas Instruments Inc

Inventors

• Nagarajan Viswanathan
• Naru Srinivas Kumar Reddy
• Parupudi Ratna Kumar Venkata

Classifications

• H03M1/168

  and delivering the same number of bits · CPC title

• H03M1/0641 Primary

  the dither being a random signal · CPC title