Memory device using comb-like routing structure for reduced metal line loading

Patent metadata

Field	Value
Publication number	US-10510415-B1
Application number	US-201816165660-A
Country	US
Kind code	B1
Filing date	Oct 19, 2018
Priority date	Sep 10, 2018
Publication date	Dec 17, 2019
Grant date	Dec 17, 2019

Abstract

A memory device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first substrate and one or more peripheral devices on the first substrate. The second semiconductor structure includes a first set of conductive lines electrically coupled with a first set of a plurality of vertical structures and a second set of conductive lines electrically coupled with a second set of the plurality of vertical structures different from the first set of the plurality of vertical structures. The first set of conductive lines are vertically distanced from one end of the plurality of vertical structures and the second set of conductive lines are vertically distanced from an opposite end of the plurality of vertical structures.

First claim

What is claimed is:

1. A memory device, comprising:
a first semiconductor structure comprising:
a first substrate;
one or more peripheral devices on the first substrate; and
one or more interconnect layers, the one or more interconnect layers comprising a first conductor layer;

a second semiconductor structure comprising:
a second substrate;
a layer stack having alternating conductor and insulator layers disposed above a first surface of the second substrate;
a plurality of structures extending vertically through the layer stack;
a first set of conductive lines electrically coupled with a first set of the plurality of structures, the first set of conductive lines being vertically distanced from one end of the plurality of structures; and
a second set of conductive lines electrically coupled with a second set of the plurality of structures different from the first set of the plurality of structures, the second set of conductive lines being vertically distanced from an opposite end of the plurality of structures.

2. The memory device of claim 1 , wherein the second semiconductor structure further comprises one or more second interconnect layers, the one or more second interconnect layers comprising a second conductor layer.

3. The memory device of claim 2 , further comprising a bond interface between the first semiconductor structure and the second semiconductor structure, wherein the first conductor layer contacts the second conductor layer at the bond interface.

4. The memory device of claim 1 , wherein the plurality of structures comprises NAND memory strings.

5. The memory device of claim 4 , wherein the first set of the plurality of structures includes a first set of the NAND memory strings and the second set of the plurality of structures includes a second set of the NAND memory strings.

6. The memory device of claim 4 , wherein the plurality of structures comprises conductive contacts.

7. The memory device of claim 6 ; wherein the first set of the plurality of structures includes only the NAND memory, strings and the second set of the plurality of structures includes only the conductive contacts.

8. The memory device of claim 1 , wherein the second set of conductive lines are located on an opposite side of the second substrate from the first set of conductive lines.

9. A memory device, comprising:
a substrate;
a layer stack having alternating conductor and insulator layers disposed above a first surface of the substrate;
a plurality of structures extending vertically through the layer stack;
a first set of conductive lines electrically coupled with a first set of the plurality of structures, the first set of conductive lines being vertically distanced from one end of the plurality of structures;
a second set of conductive lines electrically coupled with a second set of the plurality of structures different from the first set of the plurality of structures, the second set of conductive lines being vertically distanced from an opposite end of the plurality of structures;
one or more interconnect layers, the one or more interconnect layers comprising a first conductor layer at a top surface of the memory device; and
a bond interface at the top surface of the memory device, wherein a semiconductor device is configured to bond with the memory device at the bond interface.

10. The memory device of claim 9 , wherein the first conductor layer is configured to bond with a second conductor layer of the semiconductor device at the bond interface.

11. The memory device of claim 9 , wherein the plurality of structures comprises NAND memory strings.

12. The memory device of claim 11 , wherein the first set of the plurality of structures includes a first set of the NAND memory strings and the second set of the plurality of structures includes a second set of the NAND memory strings.

13. The memory device of claim 11 , wherein the plurality of structures comprises conductive contacts.

14. The memory device of claim 13 , wherein the first set of the plurality of structures includes only the NAND memory strings and the second set of the plurality of structures includes only the conductive contacts.

15. The memory device of claim 9 , wherein the second set of conductive lines are located on an opposite side of the second substrate from the first set of conductive lines.

16. A method for forming a memory device, comprising:
forming, on a first substrate, a layer stack having alternating conductor and insulator layers;
forming a plurality of structures each extending vertically through the layer stack;
forming a first set of conductive lines over one end vertically distanced from the plurality of structures, the first set of conductive lines being electrically coupled to a first set of the plurality of structures;
forming one or more peripheral devices on a second substrate;
bonding the first substrate with the second substrate at a bond interface between the first substrate and the second substrate; and
forming a second set of conductive lines over an opposite end vertically distanced from the plurality of structures, the second set of conductive lines being electrically coupled to a second set of the plurality of structures different from the first set of the plurality of structures.

17. The method of claim 16 , further comprising forming one or more interconnect layers over the plurality of structures before the bonding, the one or more interconnect layers including a first conductor layer.

18. The method of claim 17 , further comprising forming one or more second interconnect layers over the one or more peripheral devices before the bonding, the one or more second interconnect layers including a second conductor layer.

19. The method of claim 18 , wherein the first conductor layer contacts the second conductor layer during the bonding of the first substrate with the second substrate.

20. The method of claim 16 , wherein bonding the first substrate and the second substrate comprises bonding the first and second substrates using hybrid bonding.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Huo Zongliang
• Liu Jun
• Xia Zhiliang
• Xiao li hong

Classifications

• G11C16/24

  Bit-line control circuits · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C7/02

  with means for avoiding parasitic signals · CPC title

• H10W80/327

  characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers · CPC title

• H10W80/312

  characterised by the direct bonding of electrically conductive pads · CPC title