Memory device and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-2016197041-A1
Application number	US-201514589006-A
Country	US
Kind code	A1
Filing date	Jan 5, 2015
Priority date	Jan 5, 2015
Publication date	Jul 7, 2016
Grant date	—

Abstract

A memory device comprises a first conductive stripe, a first memory layer, a first conductive pillar, a first dielectric layer and a first conductive plug. The first conductive strip extends along a first direction. The first memory layer extends along a second direction adjacent to and overlapping with the first conductive stripe to define a first memory area thereon. The first conductive pillar extends along the second direction and overlapping with the first memory area. The first dielectric layer extends along the second direction adjacent to the first conductive stripe, the first memory layer and the first conductive pillar. The first conductive plus extends along the second direction and at least overlaps with a portion of the first conductive stripe, wherein the first conductive plus is electrically insulated from the first conductive stripe, the first memory layer and the first conductive pillar by the first dielectric layer.

First claim

1 . A memory device, comprising:
a first conductive stripe, extending along a first direction; a first memory layer, extending along a second direction to overlap with the first conductive stripe, so as to define a first memory area at a position where the first memory layer overlaps with first the conductive stripe; a first conductive pillar, extending adjacent to the first memory layer along the second direction and overlapping with the first memory area; a first dielectric layer, extending along the second direction and disposed adjacent to the first conductive stripe, the first memory layer and the first conductive pillar; and a first conductive plus extending along the second direction and at least overlapping with a portion of the first conductive stripe, wherein the first conductive plus is electrically insulated from the first conductive stripe, the first memory layer and the first conductive pillar by the first dielectric layer.

2 . The memory device according to claim 1 , further comprising:
a second dielectric layer, extending along the second direction and disposed adjacent to the first conductive stripe, the first memory layer and the first conductive pillar; and a second conductive plus extending along the second direction and at least overlaps with a portion of the first conductive stripe, wherein the second conductive plus is electrically insulated from the first conductive stripe, the first memory layer and the first conductive pillar by the second dielectric layer.

3 . The memory device according to claim 2 , further comprising:
a second memory layer, extending along the second direction and overlapping with the first conductive stripe, so as to define a second memory area at a position where the second memory layer overlaps with first the conductive stripe, wherein the first memory area separated from the second memory area for a first distance parallel to the first direction; and a second conductive pillar, extending adjacent to the second memory layer along the second direction and overlapping with the second memory area.

4 . The memory device according to claim 3 , further comprising:
A second conductive stripe, extending along the first direction and overlapping with the first memory layer and the second memory layer, so as to respectively define a third memory area and a fourth memory area, wherein the first conductive pillar and the second conductive pillar respectively overlap with the third memory area and the fourth memory area; and an insulating layer, extending along the first direction and disposed between the first conductive stripe and the second conductive stripe.

5 . The memory device according to claim 4 , further comprising:
a first word line, extending along a third direction and electrically contact with the first conductive pillar; and a second word line, extending along the third direction and electrically contact with the second conductive pillar; wherein the first conductive plug is disposed between the first word line and second word line and electrically insulated from the first word line and second word line.

6 . The memory device according to claim 5 , further comprising:
a first dielectric plug, disposed on the first conductive plug and in contact with the first conductive plug and the first dielectric layer; and a second dielectric plug, disposed on the second conductive plug and in contact with the second conductive plug and the second dielectric layer.

7 . The memory device according to claim 5 , further comprising:
a plurality of ridge-shaped stacks, extending along the first direction disposed on a substrate, wherein each of the ridge-shaped stacks comprises the first conductive stripe, the insulating layer and the second conductive stripe; wherein the first memory layer and the second memory layer are disposed in a trench defined by two of the ridge-shaped stacks and covers on a sidewall of the trench; the first conductive pillar and the second conductive pillar are disposed in the trench and respectively covers on the first memory layer and the second memory layer; and the first word line and the second word line are disposed on top surfaces of the ridge-shaped stacks.

8 . The memory device according to claim 4 , wherein the first conductive stripe and the second conductive stripe both comprise un-doped poly-silicon.

9 . The memory device according to claim 1 , wherein the dielectric layer has a thickness substantially ranging from 3 nm to 10 nm.

10 . The memory device according to claim 1 , further comprising:
a second memory layer, extending along the second direction to overlap with the first conductive stripe, so as to define an active area at a position where the second memory layer overlaps with first the conductive stripe; and a second conductive pillar, extending along the second direction, overlapping with the active area and connected to a string select Line (SSL).

11 . The memory device according to claim 1 , further comprising:
a second memory layer, extending along the second direction to overlap with the first conductive stripe, so as to define an active area at a position where the second memory layer overlaps with first the conductive stripe; and a second conductive pillar, extending along the second direction, overlapping with the active area and connected to a grounding select Line (GSL).

12 . A method for fabricating a memory device, comprising:
forming a multi-layer stack on a substrate; patterning the multi-layer stack to form a plurality of ridge-shaped stacks each of which at least comprises a conductive stripe extending along a first direction; forming a memory material layer on a bottom and sidewalls of a trench defined by the ridge-shaped stacks; forming a conductive material layer on the ridge-shaped stacks and fills the trench; patterning the conductive material layer and the memory material layer to define a plurality of through holes passing through the trench, so as to expose portions of the substrate and the conductive stripe, wherein the patterned memory material layer comprises at least one memory layer defined in the trench; the patterned conductive material layer comprises at least one conductive pillar defined in the trench; and a memory area is defined on a position where the memory layer overlaps with the conductive stripe; forming a dielectric layer on sidewalls of the through holes and the exposed portions of the substrate; forming a plurality of conductive plugs to partially fill the through holes respectively, so as to make each of the conductive plugs at least overlaps with a portion of the corresponding first conductive stripe; forming a plurality of dielectric plugs to fill the through holes; and patterning the conductive material layer to form at least one word line extending along a third direction on top surfaces of the ridge-shaped stacks and electrically contacting with the conductive pillar.

13 . The method according to claim 12 , wherein the forming of the through holes comprises steps of removing a portion of the conductive material layer and the memory material layer filled in the trench, whereby a portion of the conductive stripe is exposed from the sidewalls of the through holes; and the conductive pillars and the memory layers are respectively defined in the portions of the conductive material layer and the memory material layer that are remained in the trench extending along the second direction.

14 . The method according to claim 12 , wherein the patterning of the conductive material layer and the memory material layer comprises a reactive ion etching (RIE) process.

Assignees

• Macronix Int Co Ltd

Inventors

• Lai Sheng-Chih
• Chen Wei-Chen

Classifications

• H10D64/037 Primary

  comprising charge-trapping insulators · CPC title

• H01L23/53271

  Electricity · mapped topic

• H01L27/11582

  Electricity · mapped topic

• H01L21/76895

  Electricity · mapped topic

• H01L21/32136

  Electricity · mapped topic