Memory systems and methods for improved power management

Patent metadata

Field	Value
Publication number	US-10504583-B2
Application number	US-201816101480-A
Country	US
Kind code	B2
Filing date	Aug 12, 2018
Priority date	Nov 20, 2014
Publication date	Dec 10, 2019
Grant date	Dec 10, 2019

Abstract

A memory module with multiple memory devices includes a buffer system that manages communication between a memory controller and the memory devices. Each memory device supports an access mode and a low-power mode, the latter used to save power for devices that are not immediately needed. The module provides granular power management using a chip-select decoder that decodes chip-select signals from the memory controller into power-state signals that determine which of the memory devices are in which of the modes. Devices can thus be brought out of the low-power mode in relatively small numbers, as needed, to limit power consumption.

First claim

What is claimed is:

1. A memory module comprising:
a command input port to receive a module read command;
a command relay circuit coupled to the command input port to receive the module read command, the command relay circuit to issue a delayed version of the module read command from the memory module responsive to the module read command;
command logic coupled to the command input port to receive the module read command and issue a memory-device read command responsive to the module read command, the command logic including a selectable delay element to selectively impose a read-command delay on the memory-device read command;
memory devices each having a command port coupled to the command logic to receive the memory-device read command; and
a register to store a configuration value controlling the command relay circuit and the selectable delay element.

2. The memory module of claim 1 , wherein the configuration value alternatively:
powers the command relay circuit and selects a first delay through the selectable delay element; or
disables the command relay circuit and selects a second delay longer than the first delay through the selectable delay element.

3. The memory module of claim 2 , wherein the delayed version of the module read command is delayed by the second delay relative to the module read command.

4. The memory module of claim 3 , further comprising a clock input port to receive a clock signal having a clock period equal, wherein the second delay is the clock period.

5. The memory module of claim 1 , further comprising:
module data pads; and
a data buffer having memory-device data ports coupled to the memory devices to receive read data provided by the memory devices responsive to the memory-device read command and convey at least a portion of the read data to at least one of the module data pads.

6. The memory module of claim 5 , the data buffer to direct the read data to the module data pads responsive to the configuration value.

7. The memory module of claim 5 , wherein the data buffer is one of a plurality of buffers that convey the read data to the module data pads.

8. The memory module of claim 1 , wherein the memory devices are DRAM devices.

9. A method for reading data from a rank of memory devices, the rank of memory devices including a first sub-rank of memory devices on a first memory module and a second rank of memory devices on a second memory module, the method comprising:
receiving a rank read command at the first memory module;
relaying a delayed version of the rank read command to the second memory module, the delayed version of the rank read command delayed relative to the rank read command by a read-command delay;
issuing a first sub-rank read command responsive to the rank read command to the first sub-rank of memory devices on the first memory module;
issuing a second sub-rank read command time aligned with the first sub-rank read command responsive to the delayed version of the rank read command to the second sub-rank of memory devices on the second memory module; and
conveying a first portion of the read data from the first sub-rank of memory devices on the first memory module responsive to the first sub-rank read command and a second portion of the read data from the second sub-rank of memory devices on the second memory module responsive to the second sub-rank read command.

10. The method of claim 9 , wherein the conveying of the first portion of the read data from the first sub-rank of memory devices and the second portion of the read data from the second sub-rank of memory devices occur simultaneously.

11. The method of claim 9 , further comprising decoding rank chip-select signals from the rank read command.

12. The method of claim 11 , further comprising developing device chip-select signals from the decoded rank chip-select signals and simultaneously asserting the device chip-select signals to the first sub-rank of memory devices on the first memory module and the second sub-rank of memory devices on the second memory module.

13. The method of claim 9 , further comprising timing the conveying of the first portion of the read data from the first sub-rank of memory devices and the second portion of the read data from the second sub-rank of memory devices to a clock signal, the clock signal of a clock period equal to the read-command delay.

14. The method of claim 9 , further comprising loading a register on the first memory module prior to receiving the rank read command, the register loaded with a first configuration value enabling the relaying of the delayed version of the read command.

15. The method of claim 14 , wherein the first sub-rank read command is delayed responsive to the first configuration value.

16. The method of claim 15 , further comprising loading a second register on the second memory module, the second register loaded with a second configuration value different from the first configuration value while the first register is loaded with the first configuration value.

17. The method of claim 16 , wherein the second configuration value aligns the second sub-rank read command with the delayed sub-rank read command.

18. The method of claim 14 , the first configuration value assigning a number of memory devices in the first sub-rank of the memory devices.

19. The method of claim 14 , further comprising steering the first portion of the read data to alternative data pads on the first memory module responsive to the first configuration value.

20. The method of claim 19 , further comprising loading a second register on the second memory module prior to receiving the rank read command, the second register loaded with a second configuration value different from the first configuration value, and steering the second portion of the read data to alternative pads on the second memory module responsive to the second configuration value.

Assignees

• Rambus Inc

Inventors

• Ware Frederick A
• Harris James E

Classifications

• G11C8/12

  Group selection circuits, e.g. for memory block selection, chip selection, array selection · CPC title

• G11C5/063

  Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay · CPC title

• G11C11/4093 Primary

  Input/output [I/O] data interface arrangements, e.g. data buffers · CPC title

• G11C5/04

  Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports · CPC title

• G11C7/22

  Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management · CPC title