Systems and methods for gated-insulator reconfigurable non-volatile memory devices
US-2019305046-A1 · Oct 3, 2019 · US
US10497866B1 · US · B1
| Field | Value |
|---|---|
| Publication number | US-10497866-B1 |
| Application number | US-201816012430-A |
| Country | US |
| Kind code | B1 |
| Filing date | Jun 19, 2018 |
| Priority date | Jun 19, 2018 |
| Publication date | Dec 3, 2019 |
| Grant date | Dec 3, 2019 |
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A non-volatile memory device is described herein. The non-volatile memory device includes a diffusive memristor electrically coupled to a redox transistor. The redox transistor includes a gate, a source, and a drain, wherein the gate comprises a first storage element that acts as an ion reservoir, and a channel between the source and the drain comprises a second storage element, wherein a state of the memory device is represented by conductance of the second storage element.
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What is claimed is: 1. A non-volatile memory device comprising: a threshold switch; and a redox transistor that is electrically coupled to the switch, wherein the redox transistor comprises: a gate electrode that is coupled to the switch; a source electrode; a drain electrode; and a channel between the source electrode and the drain electrode, wherein the channel comprises a storage element composed of a material, the storage element is configured to emit and accept ions as a function of current that enters the gate electrode, and further wherein a state of the non-volatile memory device is a function of a redox state of the channel electrode. 2. The non-volatile memory device of claim 1 , wherein the ions are hydrogen ions. 3. The non-volatile memory device of claim 1 , wherein the switch is a diffusive memristor. 4. The non-volatile memory device of claim 3 , wherein the diffusive memristor comprises a Pt/Ag/SiO x N y /Ag/Pt stack. 5. The non-volatile memory device of claim 1 , further comprising: a second storage element coupled to the gate electrode, wherein the second storage element is composed of the material; and a solid electrolyte that is positioned between the storage element and the second storage element. 6. The non-volatile memory device of claim 5 , the material being an organic polymer. 7. The non-volatile memory device of claim 6 , wherein the organic polymer comprises poly(3,4-ethylenedioxythiophene) polystyrene sulfonate. 8. The non-volatile memory device of claim 5 , the material being a transition metal oxide. 9. The non-volatile memory device of claim 5 , wherein the material comprises at least one of MoO 3 , MoS 2 , graphene, WO 3 , TiO 2 , or LiTiO 2 . 10. The non-volatile memory device of claim 8 , wherein the electrolyte comprises Nafion. 11. The non-volatile memory device of claim 1 , wherein the threshold switch is one of a transistor, a vertical Si transistor, a Si PN diode, a Si Punchthrough diode, an Oxide PN diode, an Oxide/Nitride Schottky barrier, a varistor-type bidirectional switch, a chalcogenide threshold switch, a metal insulator metal switch, a threshold vacuum switch, or a mixed ionic electronic selector (MIEC). 12. The non-volatile memory device of claim 1 , wherein the state of the non-volatile memory is configured to be altered in response to a voltage of between 0.2V and 1V being applied to the switch. 13. The non-volatile memory device of claim 1 , wherein the non-volatile memory device is included in an array of identical non-volatile memory devices, and further wherein a hardware artificial neural network comprises the array of identical non-volatile memory devices.
Structure wherein the resistive material being in a transistor, e.g. gate · CPC title
Write characterized by the shape, e.g. form, length, amplitude of the write pulse · CPC title
Array wherein the access device being a transistor · CPC title
Write using bi-directional cell biasing · CPC title
Array wherein each memory cell has more than one access device · CPC title
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