Resistive memory device by substrate reduction

Patent metadata

Field	Value
Publication number	US-10020346-B2
Application number	US-201615162332-A
Country	US
Kind code	B2
Filing date	May 23, 2016
Priority date	May 23, 2016
Publication date	Jul 10, 2018
Grant date	Jul 10, 2018

Abstract

To provide enhanced data storage devices and systems, various systems, architectures, apparatuses, and methods, are provided herein. In a first example, a resistive memory device is provided. The resistive memory device comprises a substrate, and an active region having resistance properties that can be modified to store one or more data bits, the active region comprising region of the substrate with a chemically altered reduction level to establish a resistive memory property in the substrate. The resistive memory device comprises terminals formed into the substrate and configured to couple the active region to associated electrical contacts.

First claim

What is claimed is:

1. A resistive memory device, comprising:
a substrate comprised of a metal oxide material, wherein the substrate has a first surface and a second surface opposite the first surface;
an active region having resistance properties that can be modified to store one or more data bits, the active region comprising a region of the substrate with a chemically altered reduction level to establish a resistive memory property in the substrate, the active region in direct contact with the substrate, wherein the active region has a third surface and a fourth surface opposite the third surface;
an isolation zone coupled to the active region, wherein the isolation zone has a fifth surface in contact with the fourth surface and a sixth surface opposite the fifth surface, wherein the isolation zone is oxidized; and
terminals configured to couple the active region to associated electrical contacts, wherein the terminals comprise a source electrode and a drain electrode, wherein the source electrode has a seventh surface and an eighth surface opposite the seventh surface, wherein the drain electrode has a ninth surface and a tenth surface opposite the ninth surface, and wherein the tenth surface, the eighth surface and the sixth surface are coplanar.

2. The resistive memory device of claim 1 , wherein the terminals each comprise a region of the substrate chemically reduced to a greater reduction level than the active region to establish the conductive property in the substrate.

3. The resistive memory device of claim 1 ,
wherein the isolation zone is configured to inhibit migration of contaminants into a surface of the active region, and the isolation zone comprises a chemically oxidized layer of the active region.

4. The resistive memory device of claim 3 , comprising:
a gate portion positioned over the active region and configured to modify the resistance properties of the active region responsive to voltages applied to the gate portion, wherein the gate portion is positioned on at least one of the isolation zone and a gate oxide layer formed on top of the isolation zone.

5. The resistive memory device of claim 1 , wherein the metal oxide material of the substrate comprises at least one of an oxide of titanium, oxide of hafnium, oxide of tantalum, oxide of zirconium, oxide of tungsten, oxide of ruthenium, oxide of yttrium, oxide of scandium, oxide of cobalt, oxide of nickel, oxide of copper, perovskite material, and delafossite material.

6. The resistive memory device of claim 1 , comprising:
a semiconductor sublayer on which the substrate is layered, the semiconductor sublayer comprising logic circuitry configured to control at least the resistive memory device.

Assignees

• Western Digital Tech Inc

Inventors

• Bedau Daniel

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H01L45/1206

  Electricity · mapped topic

• H01L23/528

  Electricity · mapped topic

• H01L45/146

  Electricity · mapped topic

• H01L45/147

  Electricity · mapped topic