Wafer-level package with enhanced performance

Patent metadata

Field	Value
Publication number	US-10486963-B2
Application number	US-201715676415-A
Country	US
Kind code	B2
Filing date	Aug 14, 2017
Priority date	Aug 12, 2016
Publication date	Nov 26, 2019
Grant date	Nov 26, 2019

Abstract

The present disclosure relates to a wafer-level package that includes a first thinned die, a multilayer redistribution structure, a first mold compound, and a second mold compound. The first thinned die resides over a top surface of the multilayer redistribution structure. The multilayer redistribution structure includes at least one support pad that is on a bottom surface of the multilayer redistribution structure and vertically aligned with the first thinned die. The first mold compound resides over the multilayer redistribution structure and around the first thinned die, and extends beyond a top surface of the first thinned die to define an opening within the first mold compound and over the first thinned die. The second mold compound fills the opening and is in contact with the top surface of the first thinned die.

First claim

What is claimed is:

1. An apparatus comprising:
a first thinned die comprising a first device layer and a first dielectric layer over the first device layer, wherein the first device layer comprises a plurality of first die contacts at a bottom surface of the first device layer;
a multilayer redistribution structure comprising at least one first support pad, a plurality of package contacts, and redistribution interconnects, wherein:
the first thinned die resides over a top surface of the multilayer redistribution structure;
the at least one first support pad is on a bottom surface of the multilayer redistribution structure and vertically aligned with the first thinned die, such that the at least one first support pad is placed vertically below the first thinned die;
the plurality of package contacts are on the bottom surface of the multilayer redistribution structure; and
the redistribution interconnects connect the plurality of package contacts to certain ones of the plurality of first die contacts, wherein the at least one first support pad is not in contact with the plurality of package contacts and the redistribution interconnects, and is electrically isolated from the plurality of package contacts, the redistribution interconnects, and the plurality of first die contacts;

a first mold compound residing over the multilayer redistribution structure and around the first thinned die, and extending beyond a top surface of the first thinned die to define an opening within the first mold compound and over the first thinned die, wherein the top surface of the first thinned die is exposed at a bottom of the opening; and
a second mold compound filling the opening and in contact with the top surface of the first thinned die.

2. The apparatus of claim 1 wherein the plurality of package contacts and the at least one first support pad are formed from a common electrically conductive layer.

3. The apparatus of claim 1 wherein a bottom surface of the at least one first support pad and a bottom surface of each of the plurality of package contacts are in a same flat plane.

4. The apparatus of claim 1 further comprising at least one second support pad on the bottom surface of the multilayer redistribution structure and not placed vertically below the first thinned die, wherein the at least one second support pad is electrically isolated from the plurality of package contacts and the redistribution interconnects.

5. The apparatus of claim 4 wherein the at least one first support pad and the at least one second support pad are separate.

6. The apparatus of claim 4 wherein the at least one first support pad and the at least one second support pad are connected together.

7. The apparatus of claim 1 wherein the first thinned die provides a microelectromechanical systems (MEMS) component.

8. The apparatus of claim 1 wherein the first thinned die is formed from a silicon-on-insulator (SOI) structure, wherein the first device layer of the first thinned die is formed from a silicon epitaxy layer of the SOI structure, and the first dielectric layer of the first thinned die is a buried oxide layer of the SOI structure.

9. The apparatus of claim 1 further comprising a second intact die residing over the top surface of the multilayer redistribution structure, wherein:
the second intact die has a second device layer and an intact silicon substrate over the second device layer; and
the first mold compound encapsulates the second intact die.

10. The apparatus of claim 9 wherein the first thinned die provides a MEMS component and the second intact die provides a complementary metal-oxide-semiconductor (CMOS) controller that controls the MEMS component.

11. The apparatus of claim 9 further comprising a third thinned die residing over the top surface of the multilayer redistribution structure, wherein:
the third thinned die has a third device layer and a second dielectric layer over the third device layer;
the first mold compound extends beyond a top surface of the third thinned die to define a second opening within the first mold compound and over the third thinned die, wherein the top surface of the third thinned die is exposed at a bottom of the second opening; and
the second mold compound fills the second opening and is in contact with the top surface of the third thinned die.

12. The apparatus of claim 11 further comprising at least one second support pad and at least one third support pad, wherein:
the at least one second support pad and the at least one third support pad are on the bottom surface of the multilayer redistribution structure;
the at least one second support pad and the at least one third support pad are electrically isolated from the plurality of package contacts and the redistribution interconnects;
the at least one second support pad is not placed vertically below the first thinned die and not placed vertically below the third thinned die; and
the at least one third support pad is vertically aligned with the third thinned die, such that the at least one third support pad is placed vertically below the third thinned die.

13. The apparatus of claim 11 wherein the first thinned die provides a MEMS component, the second intact die provides a CMOS controller that controls the MEMS component, and the third thinned die is formed from an SOI structure, wherein the third device layer of the third thinned die is formed from a silicon epitaxy layer of the SOI structure, and the second dielectric layer of the third thinned die is a buried oxide layer of the SOI structure.

14. The apparatus of claim 1 wherein the multilayer redistribution structure further comprises at least one structure pad, wherein:
the at least one structure pad and the redistribution interconnects are formed from a common electrically conductive layer; and
the at least one structure pad is vertically below the first thinned die, and electrically isolated from the redistribution interconnects and the plurality of first die contacts.

15. The apparatus of claim 1 wherein the second mold compound has a thermal conductivity greater than 2 W/m·K.

16. The apparatus of claim 1 wherein the second mold compound has an electrical resistivity greater that 1 E6 Ohm-cm.

17. The apparatus of claim 1 wherein the first mold compound is formed from a same material as the second mold compound.

18. The apparatus of claim 1 wherein the first mold compound and the second mold compound are formed from different materials.

19. The apparatus of claim 1 wherein the multilayer redistribution structure is free of glass fiber.

20. The apparatus of claim 1 wherein connections between the redistribution interconnects and the plurality of first die contacts are solder-free.

21. An apparatus comprising:
a first thinned die comprising a first device layer and a first dielectric layer over the first device layer, wherein the first device layer comprises a plurality of first die contacts at a bottom surface of the first device layer;
a multilayer redistribution structure comprising at least one structure pad, a plurality of package contacts, and redistribution interconnects, wherein:
the first thinned die resides over a top surface of the multilayer redistribution structure;
the plurality of package contacts are on a bottom surface of the multilayer redistribution structure;
the redistribution interconnects connect the plurality of package contacts to certain ones of the plurality of first die contacts;
the at least one structure pad and

Assignees

• Qorvo Us Inc

Inventors

• Hatcher Jr Merrill Albert
• Hammond Jonathan Hale
• Chadwick Jon
• Costa Julio C
• Vandemeer Jan Edward

Classifications

• H10P72/743

  used as a support during manufacture of interconnect decals or build up layers · CPC title

• H10P72/74

  using temporarily an auxiliary support · CPC title

• H10W90/10

  Configurations of laterally-adjacent chips · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title