Via and skip via structures

Patent metadata

Field	Value
Publication number	US-10485111-B2
Application number	US-201715647400-A
Country	US
Kind code	B2
Filing date	Jul 12, 2017
Priority date	Jul 12, 2017
Publication date	Nov 19, 2019
Grant date	Nov 19, 2019

Abstract

The present disclosure generally relates to semiconductor structures and, more particularly, to via and skip via structures and methods of manufacture. The method includes: forming a first metallization layer with a first capping layer over the first metallization layer; forming a second metallization layer with a second capping layer over the second metallization layer; forming a partial skip via structure to the first metallization layer by removing a portion of the first capping layer and the second capping and depositing conductive material in an opening formed in the second metallization layer; forming a third capping layer over the filled partial skip via and the second capping layer; and forming a remaining portion of a skip via structure in alignment with the partial skip via structure by opening the third capping layer to expose the conductive material of the partial skip via.

First claim

What is claimed:

1. A method comprising:
forming a first metallization layer with a first capping layer over the first metallization layer;
forming a second metallization layer with a second capping layer over the second metallization layer;
etching through a first dielectric layer to the first capping layer;
forming a partial skip via structure to the first metallization layer by removing a portion of the first capping layer and the second capping layer and depositing conductive material in an opening formed in the second metallization layer;
forming a third capping layer over the filled partial skip via and directly on the second capping layer;
forming a second dielectric layer covering select metallization features of the second metallization layer; and
forming a remaining portion of a skip via structure in alignment with the partial skip via structure by opening the third capping layer to expose the conductive material of the partial skip via, wherein the third capping layer directly on the second capping layer forms a gap fill for the skip via structure.

2. The method of claim 1 , wherein the partial skip via structure is partially filled by an electroless process.

3. The method of claim 2 , wherein the electroless process comprises filling the partial skip via with Co or Ru.

4. The method of claim 1 , wherein the partial skip via structure is filled with Co or Ru by a chemical vapor deposition process.

5. The method of claim 1 , wherein the partial skip via structure is filled with the conductive material to about 80% to 90% of its height.

6. The method of claim 1 , wherein the remaining portion of the skip via structure is filled with a metal selected from the group consisting of Co, W or Al.

7. The method of claim 1 , further comprising forming a via to contact exposed metallization features of the second metallization layer in a same process as the remaining portion of the skip via structure.

8. The method of claim 7 , wherein the via and the remaining portion of the skip via structure are filled with a different material than the partial skip via structure.

9. The method of claim 8 , wherein the forming the remaining portion of the skip via structure is a self aligned process.

10. The method of claim 8 , further comprising foi wing a wiring structure in contact with the via and the remaining portion of the skip via structure using a dual damascene process.

11. The method of claim 1 , wherein the gap fill alleviates minimum insulator requirements.

12. The method of claim 11 , wherein the minimum insulator requirements are a minimum spacing between via structures.

13. The method of claim 12 , wherein the dielectric layer is a low-k dielectric material.

14. The method of claim 13 , wherein the second metallization layer is an etched metallization layer.

15. The method of claim 14 , wherein the etched metallization layer is etched using a wet process.

16. The method of claim 15 , further comprising forming a third metallization layer simultaneously with the remaining portion of the skip via structure to contact metallization features of the second metallization feature layer.

Assignees

• Globalfoundries Inc

Inventors

• Law Shao Beng
• Licausi Nicholas V
• Ryan Errol Todd
• Mcmahon James
• Smith Ryan S
• Zhang Xunyuan

Classifications

• H10W20/421

  Skip vias, i.e. vias that do not connect all metallization layers that they pass through · CPC title

• H10W20/4437

  the principal metal being a transition metal · CPC title

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10W20/087

  involving multiple stacked pre-patterned masks · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title