Latency buffer circuit with adaptable time shift

Patent metadata

Field	Value
Publication number	US-10484165-B2
Application number	US-201715846560-A
Country	US
Kind code	B2
Filing date	Dec 19, 2017
Priority date	Dec 19, 2017
Publication date	Nov 19, 2019
Grant date	Nov 19, 2019

Abstract

Data words are received in parallel in response to an edge of a master clock signal and selected for serial output in response to a select signal. For a detected temporal offset of the serially output data words, the generation of the select signal and the master clock signal are controlled to correct for the temporal offset by shifting timing of the edge of the master clock signal and adjusting a sequence of values for the select signal that are generated within one cycle of the master clock signal. For a backward temporal offset, at least one count value in the sequence of values is skipped and the edge of the master clock signal occurs earlier in time. For a forward temporal offset, at least one count value in the sequence of values is held and the edge of the master clock signal occurs later in time.

First claim

The invention claimed is:

1. A circuit, comprising:
a multiplexer having a plurality of inputs configured to receive data words in parallel and having an output configured to output selected ones of the received data words in series in response to a select signal;
a first-in first-out (FIFO) circuit configured to supply the data words in parallel in response to an edge of a master clock signal; and
a timing control circuit configured to generate the select signal and the master clock signal in response to a temporal shift signal and a system clock signal, wherein the timing control circuit responds to an assertion of the temporal shift signal by modifying a duty cycle of the master clock signal and controlling a sequence of values for the select signal.

2. The circuit of claim 1 , wherein the temporal shift signal is a forward shift signal and wherein the sequence of values for the select signal is controlled by the timing control circuit to skip at least one count value in the sequence of values for the select signal.

3. The circuit of claim 2 , wherein the timing control circuit reduces the duty cycle of the master clock signal to account for the skipping of said at least one count value in the sequence of values for the select signal.

4. The circuit of claim 2 , wherein modification of the duty cycle of the master clock signal comprises a reduction of a length of phase of the master clock signal to account for the skipping of said at least one count value in the sequence of values for the select signal.

5. The circuit of claim 2 , wherein modification of the duty cycle of the master clock signal causes a next edge of the master clock signal causing the FIFO circuit to supply the data words in parallel to occur earlier in time so as to advance multiplexer output of the selected ones of the received data words in series.

6. The circuit of claim 2 , further comprising a control circuit configured to detect a backward temporal offset of a series of data words output from the multiplexer and assert the forward shift signal.

7. The circuit of claim 1 , wherein the temporal shift signal is a backward shift signal and wherein the sequence of values for the select signal is controlled by the timing control circuit to hold at least one count value in the sequence of values for the select signal for a longer time than other count values in the sequence of values for the select signal.

8. The circuit of claim 7 , wherein the timing control circuit increases the duty cycle of the master clock signal to account for the holding of said at least one count value in the sequence of values for the select signal.

9. The circuit of claim 7 , wherein modification of the duty cycle of the master clock signal comprises an increase of a length of phase of the master clock signal to account for the holding of said at least one count value in the sequence of values for the select signal.

10. The circuit of claim 7 , wherein modification of the duty cycle of the master clock signal causes a next edge of the master clock signal causing the FIFO circuit to supply the data words in parallel to occur later in time so as to delay multiplexer output of the selected ones of the received data words in series.

11. The circuit of claim 7 , further comprising a control circuit configured to detect a forward temporal offset of a series of data words output from the multiplexer and assert the temporal shift signal.

12. A circuit, comprising:
a multiplexer having a plurality of inputs configured to receive data words in parallel and having an output configured to output selected ones of the received data words in series in response to a select signal;
a first-in first-out (FIFO) circuit configured to supply the data words in parallel in response to an edge of a master clock signal; and
a timing control circuit configured to generate the select signal and the master clock signal in response to a temporal shift signal and a system clock signal, wherein the timing control circuit responds to an assertion of the temporal shift signal by shifting timing of said edge of the master clock signal and controlling a sequence of values for the select signal that are generated within one cycle of the master clock signal.

13. The circuit of claim 12 , wherein the temporal shift signal is a forward shift signal and wherein the sequence of values for the select signal is controlled by the timing control circuit to skip at least one count value in the sequence of values for the select signal that are generated within one cycle of the master clock signal.

14. The circuit of claim 13 , wherein the timing control circuit causes the edge of the master clock signal causing the FIFO circuit to supply the data words in parallel to occur earlier in time due to the skipping of said at least one count value in the sequence of values for the select signal.

15. The circuit of claim 13 , further comprising a control circuit configured to detect a backward temporal offset of a series of data words output from the multiplexer and assert the forward shift signal.

16. The circuit of claim 12 , wherein the temporal shift signal is a backward shift signal and wherein the sequence of values for the select signal is controlled by the timing control circuit to hold at least one count value in the sequence of values for the select signal for a longer time than other count values in the sequence of values for the select signal.

17. The circuit of claim 16 , wherein the timing control circuit causes the edge of the master clock signal causing the FIFO circuit to supply the data words in parallel to occur later in time due to the holding of said at least one count value in the sequence of values for the select signal.

18. The circuit of claim 16 , further comprising a control circuit configured to detect a forward temporal offset of a series of data words output from the multiplexer and assert the backward shift signal.

19. A method, comprising:
providing a plurality of data words in parallel in response to an edge of a master clock signal;
serially selecting ones of the received plurality of data words in response to a sequence of values of a select signal;
outputting the serially selecting ones of the received plurality of data words in a serial stream of data words;
detecting a temporal offset of said serial stream of data words;
controlling the sequence of values for the select signal that are generated within one cycle of the master clock signal to:
skip at least one count value in the sequence of values if the detected temporal offset is a backward temporal offset; and
hold at least one count value in the sequence of values for a longer period of time if the detected temporal offset is a forward temporal offset; and

shifting timing of the edge of the master clock signal to account for the controlled sequence of values for the select signal.

20. The method of claim 19 , wherein shifting timing causes the edge of the master clock signal causing the plurality of data words to be provided in parallel to occur earlier in time due to the skipping of said at least one count value in the sequence of values for the select signal.

21. The method of claim 19 , wherein shifting timing causes the edge of the master clock signal causing the plurality of data words to be provided in parallel to occur later in time due to the holding of said at least one count value in the sequence of values for the select signal.

22. A method, comprising:
providing a plurality o

Assignees

• St Microelectronics Int Nv

Inventors

• Singh Rupesh
• Bal Ankur

Classifications

• H03M9/00

  Parallel/series conversion or vice versa (digital stores in which the information is moved stepwise per se G11C19/00) · CPC title

• G06F13/4291

  using a clocked protocol · CPC title

• H04J3/047 Primary

  Distributors with transistors or integrated circuits · CPC title

• H04J3/0685

  Clock or time synchronisation in a node; Intranode synchronisation · CPC title

• G06F13/42

  Bus transfer protocol, e.g. handshake; Synchronisation · CPC title