High speed serializer using quadrature clocks

Patent metadata

Field	Value
Publication number	US-10110334-B2
Application number	US-201615137187-A
Country	US
Kind code	B2
Filing date	Apr 25, 2016
Priority date	Apr 25, 2016
Publication date	Oct 23, 2018
Grant date	Oct 23, 2018

Abstract

Techniques efficiently serialize multiple data streams using quadrature clocks. Serializer employs first, second, third, and fourth clock signals. Serializer receives multiple data streams via registers, with each of four paths comprising a register, buffer, and switch, with registers of first and fourth paths associated with third clock signal, and registers of second and third paths associated with first clock signal, and with switches of first and fourth paths associated with first clock signal, and switches of second and third paths associated with third clock signal. Switches of first and second paths transfer respective data bits to fifth switch via another buffer, wherein fifth switch is associated with a delayed second clock signal of a time delay component (TDC). Switches of third and fourth paths transfer respective data bits to sixth switch via another buffer, wherein sixth switch is associated with a delayed fourth clock signal of TDC.

First claim

What is claimed is:

1. A data transmitting system, comprising:
a serializer component that is configured to convert multiple data streams to a serialized data stream based at least in part on quadrature clock signals comprising a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal, the multiple data streams comprising a first data stream, a second data stream, a third data stream, and a fourth data stream; and
a time delay component that is configured to generate a first time-delayed clock signal based at least in part on the second clock signal, and generates a second time-delayed clock signal based at least in part on the fourth clock signal, the time delay component providing the first time-delayed clock signal to a switch associated with the first data stream and the second data stream to facilitate control of switching of the switch, and providing the second time-delayed clock signal to another switch associated with the third data stream and the fourth data stream to facilitate control of switching of the other switch.

2. The system of claim 1 , wherein the serializer component comprises an input component that receives the multiple data streams in parallel.

3. The system of claim 1 , wherein first data of the first data stream received by a first input sub-component is transferred by the first input sub-component to a first switch in response to the third clock signal associated with the first input sub-component being at a first level, wherein second data of the second data stream received by a second input sub-component is transferred by the second input sub-component to a second switch in response to the first clock signal associated with the second input sub-component being at the first level, wherein third data of the third data stream received by a third input sub-component is transferred by the third input sub-component to a third switch in response to the first clock signal associated with the third input sub-component being at the first level, and wherein fourth data of the fourth data stream received by a fourth input sub-component is transferred by the fourth input sub-component to a fourth switch in response to the third clock signal associated with the fourth input sub-component being at the first level.

4. The system of claim 1 , wherein a buffer component is associated with a first data path and a second data path, wherein another buffer component is associated with a third data path and a fourth data path, wherein the switch is associated with the buffer component, and wherein the other switch is associated with the other buffer component.

5. The system of claim 4 , wherein first data of the first data stream received by a first switch associated with the first data path is transferred by the first switch to the switch in response to the first clock signal associated with the first switch being at a first level, and wherein the switch transfers the first data to an output buffer to facilitate the generation of the serialized data stream in response to the first time-delayed clock signal associated with the switch being at the first level.

6. The system of claim 4 , wherein second data of the second data stream received by a second switch associated with the second data path is transferred by the second switch to the switch in response to the third clock signal associated with the second switch being at the first level, and wherein the switch transfers the second data to an output buffer to facilitate the generation of the serialized data stream in response to the first time-delayed clock signal associated with the switch being at the first level.

7. The system of claim 4 , wherein third data of the third data stream received by a third switch associated with the third data path is transferred by the third switch to the other switch in response to the third clock signal associated with the third switch being at the first level, and wherein the other switch transfers the third data to an output buffer to facilitate the generation of the serialized data stream in response to the second time-delayed clock signal associated with the other switch being at the first level.

8. The system of claim 4 , wherein fourth data of the fourth data stream received by a fourth switch associated with the fourth data path is transferred by the fourth switch to the other switch in response to the first clock signal associated with the fourth switch being at the first level, and wherein the other switch transfers the fourth data to an output buffer to facilitate the generation of the serialized data stream in response to the second time-delayed clock signal associated with the other switch being at the first level.

9. The system of claim 1 , wherein the first clock signal has a first time cycle, the second clock signal has a second time cycle that begins a quarter of a time cycle after a beginning of the first time cycle, the third clock signal has a third time cycle that begins a half of the time cycle after the beginning of the first time cycle, and the fourth clock signal has a fourth time cycle that begins a three-quarter of the time cycle after the beginning of the first time cycle.

10. The system of claim 1 , wherein the serializer component is associated with a device, wherein the device comprises a transceiver, a transmitter, a digital-to-analog converter, a router, or a modem.

11. A data transmitting method, comprising:
converting multiple data streams to a serialized data stream based at least in part on quadrature clock signals comprising a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal, the multiple data streams comprising a first data stream, a second data stream, a third data stream, and a fourth data stream;
generating a first matching delay clock signal based at least in part on the second clock signal, the first matching delay clock signal being provided to a switch associated with the first data stream and the second data stream to facilitate controlling switching of the switch to facilitate the converting; and
generating a second matching delay clock signal based at least in part on the fourth clock signal, the second matching delay clock signal being provided to another switch associated with the third data stream and the fourth data stream to facilitate the controlling of the switching of the other switch to facilitate the converting.

12. The method of claim 11 , further comprising:
receiving the multiple data streams simultaneously.

13. The method of claim 11 , further comprising:
transferring first data of the first data stream to a first switch in response to the third clock signal being at a defined level;
transferring second data of the second data stream to a second switch in response to the first clock signal being at the defined level;
transferring third data of the third data stream to a third switch in response to the first clock signal being at the defined level; and
transferring fourth data of the fourth data stream to a fourth switch in response to the third clock signal being at the defined level.

14. The method of claim 13 , further comprising:
in response to the first clock signal associated with the first switch being at the defined level, switching the first switch to an open state to enable the first data received by the first switch to be transferred to the switch; and
in response to the first matching delay clock signal associated with the switch being at the defined level, switching the switch to the open state to enable the first data received by the switch to be transferred to an output buffer to facilitate generati

Assignees

• Applied Micro Circuits Corp
• Macom Connectivity Solutions Llc

Inventors

• Gupta Vijay
• Gupta Tarun

Classifications

• H04L7/0037

  Delay of clock signal · CPC title

• H04J3/0691 Primary

  Synchronisation in a TDM node · CPC title

• H04J3/047

  Distributors with transistors or integrated circuits · CPC title

• H04J3/0685

  Clock or time synchronisation in a node; Intranode synchronisation · CPC title

• H03M9/00 Primary

  Parallel/series conversion or vice versa (digital stores in which the information is moved stepwise per se G11C19/00) · CPC title