Latency control in a transmitter/receiver buffer

Patent metadata

Field	Value
Publication number	US-9509640-B2
Application number	US-201414561452-A
Country	US
Kind code	B2
Filing date	Dec 5, 2014
Priority date	Dec 5, 2014
Publication date	Nov 29, 2016
Grant date	Nov 29, 2016

Abstract

In a method for buffering, a buffer buffers data responsive to read and write clock signals. A flag signal from the buffer is for a fill level thereof. The flag signal is toggled responsive to the data buffered being either above or below a set point for the fill level. A phase of the write clock signal is adjusted to a phase of the read clock signal responsive to the toggling of the flag signal. The write clock signal is used to control latency of the buffer. The adjusting of the phase of the write clock signal includes: generating an override signal responsive to the toggling of the flag signal; and inputting the read clock signal and the override signal to a phase adjuster to controllably adjust the phase of the write clock signal to the phase of the read clock signal during operation.

First claim

What is claimed is:

1. A method for buffering, comprising:
operating a buffer to buffer data responsive to a read clock signal and a write clock signal provided to the buffer;
obtaining a flag signal from the buffer responsive to fill level of the buffer by a state machine;
toggling the flag signal responsive to the data buffered being either above or below a set point for the fill level;
adjusting a phase of the write clock signal to a phase of the read clock signal responsive to the toggling of the flag signal; and
outputting the write clock signal for the operating of the buffer with controlled latency thereof, wherein the latency of the buffer is controlled responsive to the adjusting;
wherein the adjusting of the phase of the write clock signal comprises:
generating an override signal by the state machine responsive to the toggling of the flag signal; and
inputting the read clock signal and the override signal to a phase adjuster to controllably adjust the phase of the write clock signal to the phase of the read clock signal during the operating of the buffer;
wherein the phase adjuster is configured to adjust delay of the read clock signal responsive to the override signal to align the phase of the write clock signal to the phase of the read clock signal for the adjusting.

2. The method according to claim 1 , wherein the phase of the write clock signal is adjusted by adjustment of the delay for the set point of the fill level of the buffer at a half full level.

3. The method according to claim 1 , further comprising resetting the buffer.

4. The method according to claim 1 , further comprising switching from a buffer bypass mode to a buffer operation mode for operation of the buffer.

5. The method according to claim 1 , further comprising:
receiving a reference clock signal by a phase interpolator;
adjusting frequency of a parallel-input, serial-output clock signal by the phase interpolator during the operating of the buffer; and
obtaining the read clock signal from the parallel-input, serial-output clock signal sourced from the phase interpolator.

6. The method according to claim 5 , wherein the read clock signal is a divided down version of the parallel-input, serial-output clock signal.

7. The method according to claim 6 , further comprising instantiating the state machine in programmable resources as a finite state machine.

8. The method according to claim 1 , wherein the phase adjuster comprises a delay aligner.

9. The method according to claim 1 , wherein the phase adjuster comprises a phase controller of a clock module.

10. A system for data processing and communication, comprising:
input circuitry coupled to receive multiple data source inputs;
a plurality of transmitters respectively providing clock signals for the multiple data source inputs and respectively coupled to receive channelized data streams for the multiple data source inputs from the input circuitry;
wherein the input circuitry and the plurality of transmitters are of a single integrated circuit package;
wherein the plurality of transmitters respectively include phase interpolators for frequency adjustment to respectively provide the clock signals;
wherein the plurality of transmitters respectively include transmit buffers coupled to provide controlled latencies respectively thereof; and
wherein each of the plurality of transmitters comprises:
a transmit buffer configured to input data responsive to a write clock signal, output the data buffer responsive to a read clock signal, and provide a flag signal responsive to a fill level of the transmit buffer; and
a delay aligner configured to controllably adjust a phase of the write clock signal to a phase of the read clock signal to provide the write clock signal for the transmit buffer for controlled latency of the transmit buffer responsive to adjustment of the phase of the write clock signal.

11. The system according to claim 10 , wherein the integrated circuit package further comprises a plurality of digital phase-locked loops respectively coupled to receive the clock signals and further respectively coupled to the plurality of transmitters to provide control signals thereto.

12. The system according to claim 11 , wherein each of the plurality of transmitters is coupled to receive at least one external reference signal with a clock pattern.

13. The system according to claim 11 , wherein each of the plurality of transmitters further comprises:
a state machine coupled to receive the flag signal from the transmit buffer to generate an override signal;
wherein the delay aligner is coupled to receive the read clock signal and the override signal from the state machine to provide the write clock signal; and
wherein the delay aligner is coupled to controllably adjust the phase of the write clock signal to the phase of the read clock signal responsive to the override signal to provide the write clock signal for the transmit buffer for the controlled latency thereof.

14. A transmitter, comprising:
a transmit buffer coupled to input data to buffer responsive to a write clock signal and to output the data buffered responsive to a read clock signal;
a state machine coupled to receive a flag signal from the transmit buffer to generate an override signal;
a delay aligner coupled to receive the read clock signal and the override signal from the state machine to provide the write clock signal;
wherein the transmit buffer is coupled to provide the flag signal responsive to a fill level of the transmit buffer;
wherein the delay aligner is coupled to controllably adjust a phase of the write clock signal to a phase of the read clock signal responsive to the override signal to provide the write clock signal for the transmit buffer; and
wherein latency of the transmit buffer is controlled responsive to adjustment of the phase of the write clock signal.

15. The transmitter according to claim 14 , further comprising:
a phase interpolator coupled to receive a reference clock signal;
wherein the phase interpolator is coupled to adjust frequency of a parallel-input, serial-output clock signal responsive to the reference clock signal; and
divider block coupled to receive the parallel-input, serial-output clock signal from the phase interpolator to provide the read clock signal as a divided down version of the parallel-input, serial-output clock signal.

16. The transmitter according to claim 15 , further comprising:
a parallel-to-serial converter coupled to the transmit buffer to receive the data therefrom responsive to the read clock signal;
wherein the read clock signal is provided to the parallel-to-serial converter as an input clock signal.

17. The transmitter according to claim 16 , wherein the divider block is coupled to provide an output clock signal to the parallel-to-serial converter.

18. The transmitter according to claim 16 , further comprising a multiplexer coupled to receive the write clock signal from the delay aligner and further coupled to receive the read clock signal from the divider block to select either as the write clock signal to provide to the transmit buffer.

19. The transmitter according to claim 18 , further comprising a clock driver coupled to the multiplexer to receive the write clock signal selected to provide to the transmit buffer.

20. The transmitter according to claim 19 , wherein the phase of the read clock signal is static.

Assignees

• Xilinx Inc

Inventors

• Taylor David F
• Klein Matthew H
• Vendramini Vincent

Classifications

• G06F5/12

  Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations · CPC title

• G06F2205/126

  Monitoring of intermediate fill level, i.e. with additional means for monitoring the fill level, e.g. half full flag, almost empty flag · CPC title

• H03L7/06

  using a reference signal applied to a frequency- or phase-locked loop · CPC title

• H04B1/44

  Transmit/receive switching · CPC title

• H03L7/07

  using several loops, e.g. for redundant clock signal generation · CPC title