Tray for aligning semiconductor packages and test handler using the same, and method of aligning semiconductor packages and test method using the same
US-9459315-B2 · Oct 4, 2016 · US
Chip accommodation tray
US10475681B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10475681-B2 |
| Application number | US-201615373795-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 9, 2016 |
| Priority date | Dec 24, 2015 |
| Publication date | Nov 12, 2019 |
| Grant date | Nov 12, 2019 |
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- Title
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- Abstract
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Abstract
Official abstract text for this publication.
A chip accommodation tray for accommodating a plurality of chips includes a holding sheet for holding the chips on a face side thereof, the holding sheet having a tack force and a plurality of first pores formed therethrough, and a frame including a bottom wall supporting a reverse side of the holding sheet, the bottom wall having a plurality of second pores formed therethrough, and side walls erected from the bottom wall in surrounding relation to the holding sheet. Air is supplied from below the bottom wall of the frame through the second pores and the first pores and ejected toward lower surfaces of the chips held on the holding sheet, thereby peeling the chips off the holding sheet.
First claim
Opening claim text (preview).
What is claimed is: 1. A chip accommodation tray for accommodating a plurality of chips, comprising: a holding sheet for holding the chips on a face side thereof, the holding sheet having a tack force and a plurality of first pores formed therethrough, wherein the plurality of first pores are configured and arranged such that when the chips are accommodated in the tray, each of the chips is positioned on a plurality of the first pores; and a frame including a bottom wall supporting a reverse side of the holding sheet, the bottom wall having a plurality of second pores formed therethrough, and side walls erected from the bottom wall in surrounding relation to the holding sheet; wherein air supplied from below the bottom wall of the frame through the second pores and the first pores is ejected toward lower surfaces of the chips held on the holding sheet, thereby peeling the chips off the holding sheet. 2. The chip accommodation tray according to claim 1 , wherein said frame and said bottom wall are formed of the same material. 3. The chip accommodation tray according to claim 1 , wherein said frame and said bottom wall are integrally formed as a single component. 4. The chip accommodation tray according to claim 1 , wherein said reverse side of the holding sheet is supported in its entirety by said bottom wall of said frame. 5. The chip accommodation tray according to claim 1 , wherein said bottom wall of said frame includes a first pair of engaging cavities along one side thereof and a second pair of engaging cavities along an opposite side thereof, wherein said engaging cavities are configured and arranged for engaging support members of a transporting apparatus.
Assignees
Inventors
Classifications
- H10P72/0442Primary
Apparatus for placing on an insulating substrate, e.g. tape · CPC title
using vacuum or suction, e.g. Bernoulli chucks · CPC title
using temporarily an auxiliary support · CPC title
- H10P72/16Primary
Trays for chips · CPC title
- H10P72/165Primary
characterised by a material, a roughness, a coating or the like · CPC title
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- What does patent US10475681B2 cover?
- A chip accommodation tray for accommodating a plurality of chips includes a holding sheet for holding the chips on a face side thereof, the holding sheet having a tack force and a plurality of first pores formed therethrough, and a frame including a bottom wall supporting a reverse side of the holding sheet, the bottom wall having a plurality of second pores formed therethrough, and side walls …
- Who is the assignee on this patent?
- Disco Corp
- What technology area does this patent fall under?
- Primary CPC classification H10P72/0442. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Nov 12 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).