Adaptive read retry optimization

Patent metadata

Field	Value
Publication number	US-10469103-B1
Application number	US-201715491453-A
Country	US
Kind code	B1
Filing date	Apr 19, 2017
Priority date	Apr 19, 2017
Publication date	Nov 5, 2019
Grant date	Nov 5, 2019

Abstract

Systems, devices, and methods are presented that allow a data channel to adaptively vary a change in a reference voltage used to read data from a solid state memory. The change in the reference voltage may be determined based on a measured error statistic of the solid state memory. A hard decision low density parity check (HLDPC) decoder may be utilized in conjunction with a soft decision low density parity check (SLDPC).

First claim

What is claimed is:

1. A data storage device comprising:
a data channel circuit including:
a read circuit configured to read a cell in a solid state memory device via a reference voltage (V ref );
a first decoder configured to perform a first decoding of selected data based on read logic applying the V ref ;
an adaptation circuit configured to selectively shift the V ref by an amount, V Delta , to produce a shifted voltage reference value (V ref_shifted );
a second decoder configured to perform a second decoding of the selected data utilizing the V ref_shifted as a read voltage value by the read circuit when the first decoder cannot successfully decode the selected data; and
a calculation circuit configured to calculate and vary V Delta adaptively based on a measured error statistic of the solid state memory device.

2. The data storage device of claim 1 further comprising:
the solid state memory device;
the second decoder is configured to perform further decoding attempts of the selected data with each of the further decoding attempts utilizing an adaptively calculated V Delta .

3. The data storage device of claim 2 further comprising:
the calculation circuit further configured to calculate V Delta based on a bit error rate.

4. The data storage device of claim 3 further comprising:
the calculation circuit further configured to calculate V Delta based on a log likelihood ratio lookup table that indicates a number of errors with respect to a selected page.

5. The data storage device of claim 2 further comprising:
a tracking circuit configured to track a bit error rate over multiple Vrefs and provide a selected Vref to the calculation circuit.

6. The data storage device of claim 5 further comprising:
the tracking circuit configured to update the bit error rate based on a determined bit error rate with respect to a specific Vref.

7. The data storage device of claim 5 further comprising:
the tracking circuit configured to perform tracking via iterative hard decision decoding tracking.

8. The data storage device of claim 2 further comprising:
the first decoder includes a hard decision low density parity check (HLDPC) decoder; and
the second decoder includes a soft decision low density parity check (SLDPC) decoder.

9. A method comprising:
performing, via a first decoder, a first decoding of selected data based on read logic applying a reference voltage (V ref ) to a solid state memory;
selectively shifting the V ref by an amount, V Delta , to produce a shifted voltage reference value (V ref_shifted );
performing, via a second decoder, a second decoding of the selected data utilizing the V ref_shifted as a read voltage value when the first decoding did not successfully decode the selected data; and
adaptively calculating V Delta based on a measured error statistic of the solid state memory.

10. The method of claim 9 further comprising:
performing further decoding attempts of the selected data with each of the further decoding attempts utilizing a unique calculated V Delta .

11. The method of claim 9 further comprising:
the first decoder includes a hard decision low density parity check (HLDPC) decoder; and
the second decoder includes a soft decision low density parity check (SLDPC) decoder.

12. The method of claim 9 further comprising:
calculating V Delta based on one of a bit error rate calculation and a syndrome weight calculation.

13. An apparatus comprising:
a controller configured to read data in a solid state memory device via a reference voltage (V ref );
a hard-decision decoder configured to perform a first decoding of a selected data based on read logic applying the V ref ;
an adaptation circuit configured to selectively shift the V ref by an amount, V Delta , to produce a shifted voltage reference value (V ref_shifted );
soft-decision decoder configured to perform a second decoding of the selected data utilizing the V ref_shifted as a read voltage value by the controller when the hard-decision decoder cannot successfully decode the selected data; and
a calculation circuit configured to calculate and vary V Delta adaptively based on a measured error statistic of the solid state memory device.

14. The apparatus of claim 13 further comprising:
the soft-decision decoder configured to perform further decoding attempts of the selected data with each of the further decoding attempts utilizing an adaptively calculated V Delta .

15. The apparatus of claim 14 further comprising:
the calculation circuit further configured to calculate V Delta based on bit error rate.

16. The apparatus of claim 15 further comprising:
the calculation circuit further configured to calculate V Delta based on a log likelihood ratio lookup table that indicates a number of errors with respect to a selected page.

17. The apparatus of claim 14 further comprising:
a tracking circuit configured to track a bit error rate (BER) over multiple Vrefs and provide a selected Vref to the calculation circuit.

18. The apparatus of claim 17 further comprising:
the tracking circuit configured to update a bit error rate profile based on a determined BER with respect to a specific Vref.

19. The apparatus of claim 17 further comprising:
the tracking circuit configured to perform tracking via iterative hard decision decoding tracking.

20. The apparatus of claim 17 further comprising:
the tracking configured to perform tracking via syndrome weight tracking where the syndrome weight is calculated based on a single iteration of a hard low density parity check (LDPC) decoding.

21. The apparatus of claim 14 further comprising:
the solid state memory device;
the apparatus is part of a data channel circuit within a data storage device including the solid state memory device; and
the calculation circuit calculates and varies V Delta in real time during use of the data channel circuit when reading data from the solid state memory.

Assignees

• Seagate Technology Llc

Inventors

• Jeong Seongwook
• Alhussien Abdelhakim
• Haratsch Erich Franz

Classifications

• H03M13/1108 Primary

  Hard decision decoding, e.g. bit flipping, modified or weighted bit flipping · CPC title

• H03M13/3715

  Adaptation to the number of estimated errors or to the channel state · CPC title

• H03M13/1111

  Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms · CPC title

• H03M13/1125 Primary

  using different domains for check node and bit node processing, wherein the different domains include probabilities, likelihood ratios, likelihood differences, log-likelihood ratios or log-likelihood difference pairs · CPC title

• H03M13/6566

  Implementations concerning memory access contentions · CPC title