Method and apparatus for encoding and decoding data in memory system

Patent metadata

Field	Value
Publication number	US-9792176-B2
Application number	US-201514941051-A
Country	US
Kind code	B2
Filing date	Nov 13, 2015
Priority date	Nov 13, 2015
Publication date	Oct 17, 2017
Grant date	Oct 17, 2017

Abstract

A memory system includes a memory controller; and a memory device, the memory device including a memory cell array, the memory cell array including least a first memory page having a plurality of memory cells storing a plurality of stored bits, the memory controller being such that, the memory controller performs a first hard read operation on the first memory page to generate a plurality of read bits corresponding to the plurality of stored bits, and if the memory controller determines to change a value of one of a first group of bits, from among the plurality of read bits, the memory controller selects one of the first group of bits based on log likelihood ratio (LLR) values corresponding, respectively, to each of the first group of bits, and changes the value of the selected bit.

First claim

What is claimed is:

1. A memory system comprising:
a memory controller; and
a memory device,
the memory device including a memory cell array,
the memory cell array including least a first memory page having a plurality of memory cells storing a plurality of stored bits,
the memory controller being configured such that,
the memory controller performs a first hard read operation on the first memory page to generate a plurality of read bits corresponding to the plurality of stored bits,
the memory controller generates an operation value,
the memory controller determines, based on the operation value, whether or not to change a value of one of a first group of bits, the first group of bits being bits from among the plurality of read bits, and
if the memory controller determines to change a value of one of the first group of bits, the memory controller selects one of the first group of bits based on log likelihood ratio (LLR) values corresponding, respectively, to each of the first group of bits, and changes the value of the selected bit.

2. The memory system of claim 1 , wherein the memory controller is further configured such that,
the memory controller performs a first Bose-Chaudhuri-Hocquenghem (BCH) error correcting code (ECC) decoding operation to correct errors among the plurality of read bits generated by the first hard read operation, and
when the memory controller determines to change one of the first group of bits,
the memory controller performs a second BCH ECC decoding operation on the plurality of read bits, including the selected bit the value of which was changed, to correct additional errors among the plurality of read bits.

3. The memory system of claim 2 wherein the first memory page is configured such that,
the plurality of stored bits are arranged in a plurality of rows and a plurality of columns, the plurality of rows including a plurality of data frames and at least one parity frame,
the at least one parity frame includes a plurality of parity values corresponding, respectively, to a plurality of column groups, each of the plurality of column groups including at least one of the plurality of columns of the first memory page, and
each one of the plurality of parity values is the result of an XOR operation performed on each of the bits, from among the stored bits, that are included in one of the data frames and included in the column group to which the parity value corresponds.

4. The memory system of claim 3 , wherein the memory controller is configured to designate each of the plurality of data frames as being one of one or more error frames or one of or more correct frames, based on the results of at least one of the first and second BCH ECC decoding operations.

5. The memory system of claim 4 , wherein the memory controller is configured such that,
the first group of bits are bits, from among the read bits, that correspond to a first group of stored bits,
the first group of stored bits are bits, from among the plurality of stored bits, that are included in a first column group from among the plurality of column groups,
each bit of the first group of stored bits is included in a data frame from among the one or more error frames, and
the memory controller obtains, as the operation value, a value generated based on a result of performing an XOR operation on,
the parity value, from among the plurality of parity values, that corresponds to the first column group, and
first correct bits, the first correct bits being bits that are included in the first column group and are not included in a data frame from among the one or more error frames.

6. The memory system of claim 5 , wherein the memory controller is configured such that,
the memory controller generates a comparison result based on the operation value and a result of an XOR operation performed on the first group of bits, and
the memory controller determines whether or not to change the value of one of the first group of bits based on the comparison result.

7. A memory system comprising:
a memory controller; and
a memory device, the memory device including a memory cell array,
the memory cell array including least a first memory page having a plurality of memory cells,
the memory controller being configured to,
receive a plurality of bits from an external device,
generate a plurality of first data code words by performing error correcting code (ECC) encoding on the received plurality bits, each of the plurality of first data code words including first data bits and first redundancy bits, the first redundancy bits providing an initial error correction capability with respect to the first data bits,
store the plurality of first data code words, respectively, as a plurality of data frames in the first memory page, and
generate delta syndrome data, the generated delta syndrome data including at least a plurality of first stage delta syndromes corresponding to the plurality of first data code words, respectively, such that,
for each first data code word, of the plurality of first data code words, the first stage delta syndrome that corresponds to the first data code word provides a first stage error correction capability, the first stage error correction capability being an additional error correction capability with respect to the initial error correction capability provided by the first redundancy bits of the first data code word.

8. The memory system of claim 7 , wherein the memory controller is configured to generate the plurality of first data code words by performing Bose-Chaudhuri-Hocquenghem (BCH) ECC encoding such that the plurality of first data code words are BCH code words.

9. The memory system of claim 7 , wherein the memory controller is configured such that,
the generated delta syndrome data generated by the memory controller includes, for each of the plurality of first data code words, N stages of delta syndromes, N being a positive integer,
delta syndromes of different stages among the N stages of delta syndromes having different additional error correction capabilities with respect to the initial error correction capability provided by the first redundancy bits of the first data code words to which the delta syndromes of different stages among the N stages of delta syndromes correspond,
delta syndromes of the same stage among the N stages of delta syndromes having the same additional error correction capabilities with respect to the initial error correction capability provided by the first redundancy bits of the first data code words to which the delta syndromes of same stage among the N stages of delta syndromes correspond.

10. The memory system of claim 9 wherein,
the memory controller is configured to generate N stages of second code words corresponding, respectively, to the N stages of delta syndromes such that,
the second code words are Reed-Solomon (RS) code words each including second redundancy bits,
a stage i second code word, among the N stages of second code words, is generated by performing RS encoding on stage i delta syndromes, among the N stages of delta syndromes, and
a total number of the second redundancy bits included in a second code word, from among the N stages of second code words, is inversely related to a total number of bits the additional error correction capability of one of the delta syndromes encoded by the second code word is capable of correcting.

11. The memory system of claim 10 wherein,
the memory controller is configured to generate a projected overhead protection code word by performing an ECC encoding operation on the second redundancy bits of each of the N stages of second code words, and
the memory controller is

Assignees

• Samsung Electronics Co Ltd

Inventors

• Blaichman Evgeny
• Twitto Moshe
• Dor Avner
• Erez Elona
• Kong Jun Jin
• Landis Shay
• Shany Yaron
• Shereshevski Yoav

Classifications

• H03M13/1515

  Reed-Solomon codes · CPC title

• G06F3/0619

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0653

  Monitoring storage devices or systems · CPC title

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title