Controller, semiconductor memory system, data storage system and operating method thereof

Patent metadata

Field	Value
Publication number	US-9680504-B2
Application number	US-201514634182-A
Country	US
Kind code	B2
Filing date	Feb 27, 2015
Priority date	Oct 21, 2014
Publication date	Jun 13, 2017
Grant date	Jun 13, 2017

Abstract

An operating method of a controller includes iterating a first ECC decoding on a codeword read from a semiconductor memory device according to a first read voltage a predetermined iteration number until the first ECC decoding succeeds, wherein a value of the first read voltage is updated on basis of a number of an unsatisfied syndrome check (USC); and when the first ECC decoding fails until the predetermined iteration number, performing a second ECC decoding on the codeword by generating soft decision data according to the first read voltage, a value of which corresponds to the minimum number of the USC among the updated values during the iterating of the first ECC decoding.

First claim

What is claimed is:

1. An operating method of a controller, comprising:
iterating a first ECC decoding on a codeword read from a semiconductor memory device by generating hard decision data according to a hard decision read voltage by a predetermined iteration number until the first ECC decoding succeeds, wherein a value of the hard decision read voltage is updated on basis of a number of an unsatisfied syndrome check (USC); and
when the first ECC decoding fails until the predetermined iteration number, performing a second ECC decoding on the codeword by generating soft decision data according to the hard decision read voltage, a value of which corresponds to the minimum number of the USC among the updated values during the iterating of the first ECC decoding.

2. The operating method of the controller of claim 1 , wherein the first ECC decoding is a low density parity check (LDPC) decoding.

3. The operating method of the controller of claim 2 , wherein the USC is a nonzero element of a vector generated by a syndrome check of the LDPC decoding.

4. An operating method of a controller, comprising:
a first step of performing a first ECC decoding on a codeword read from a semiconductor memory device by generating hard decision data according to a hard decision read voltage;
a second step of determining the first ECC decoding to have failed or succeeded based on an unsatisfied syndrome check (USC) included in a result of the first ECC decoding;
a third step of updating a value of the hard decision read voltage based on a number of the USC when the first ECC decoding is determined to have failed; and
a fourth step of iterating the first to third steps by a predetermined iteration number until the first ECC decoding succeeds.

5. The operating method of the controller of claim 4 , further comprising:
a fifth step of performing a second ECC decoding on the codeword by generating soft decision data according to the hard decision read voltage, a value of which corresponds to the minimum number of the USC among the updated values during the fourth step, when the first ECC decoding fails until the predetermined iteration number.

6. The operating method of the controller of claim 4 , wherein the first ECC decoding is a low density parity check (LDPC) decoding.

7. A controller comprising:
an ECC unit detecting and correcting an error included in data read from a semiconductor memory device,
wherein the ECC unit:
iterates a first ECC decoding on a codeword read from a semiconductor memory device by generating hard decision data according to a hard decision read voltage by a predetermined iteration number until the first ECC decoding succeeds, wherein a value of the hard decision read voltage is updated on basis of a number of an unsatisfied syndrome check (USC); and
performs a second ECC decoding on the codeword by generating soft decision data according to the hard decision read voltage, a value of which corresponds to the minimum number of the USC among the updated values during the iteration of the first ECC decoding, when the first ECC decoding fails until the predetermined iteration number.

8. The controller of claim 7 , wherein the first ECC decoding is a low density parity check (LDPC) decoding.

9. The controller of claim 8 , wherein the USC is a nonzero element of a vector generated by a syndrome check of the LDPC decoding.

10. A controller comprising:
an ECC unit detecting and correcting an error included in data read from a semiconductor memory device,
wherein the ECC unit:
(1) performs a first ECC decoding on a codeword read from a semiconductor memory device by generating hard decision data according to a hard decision read voltage;
(2) determines the first ECC decoding to have failed or succeeded on the basis of an unsatisfied syndrome check (USC) included in a result of the first ECC decoding; and
(3) updates a value of the hard decision read voltage based on a number of the USC when the first ECC decoding is determined to have failed,
(4) iterates the operations of (1) to (3) by a predetermined iteration number until the first ECC decoding succeeds.

11. The controller of claim 10 ,
wherein the ECC unit performs a second ECC decoding on the codeword by generating soft decision data according to the hard decision read voltage, a value of which corresponds to the minimum number of the USC among the updated values during the iterating of the operations of the first to third means, when the first ECC decoding fails until the predetermined iteration number.

12. The controller of claim 10 , wherein the first ECC decoding is a low density parity check (LDPC) decoding.

13. A semiconductor memory system comprising:
a semiconductor memory device; and
a controller,
wherein the controller:
iterates a first ECC decoding on a codeword read from a semiconductor memory device by generating hard decision data according to a hard decision read voltage by a predetermined iteration number until the first ECC decoding succeeds, wherein a value of the hard decision read voltage is updated on basis of a number of an unsatisfied syndrome check (USC); and
performs a second ECC decoding on the codeword by generating soft decision data according to the hard decision read voltage, a value of which corresponds to the minimum number of the USC among the updated values during the iterating of the first ECC decoding, when the first ECC decoding fails until the predetermined iteration number.

14. The semiconductor memory system of claim 13 , wherein the first ECC decoding is a low density parity check (LDPC) decoding.

15. The semiconductor memory system of claim 14 , wherein the USC is a nonzero element of a vector generated by a syndrome check of the LDPC decoding.

16. A semiconductor memory system comprising:
a semiconductor memory device; and
a controller,
wherein the controller:
(1) performs a first ECC decoding on a codeword read from a semiconductor memory device by generating hard decision data according to a hard decision read voltage;
(2) determines the first ECC decoding to have failed or succeeded on the basis of an unsatisfied syndrome check (USC) included in a result of the first ECC decoding;
(3) updates a value of the hard decision read voltage based on a number of the USC when the first ECC decoding is determined to have failed, and
(4) iterates the operations of (1) to (3) by a predetermined iteration number until the first ECC decoding succeeds.

17. The semiconductor memory system of claim 16 , wherein the controller performs a second ECC decoding on the codeword by generating soft decision data according to the hard decision read voltage, a value of which corresponds to the minimum number of the USC among the updated values during the iterating of the operations of (1) to (3), when the first ECC decoding fails until the predetermined iteration number.

18. The semiconductor memory system of claim 16 , wherein the first ECC decoding is a low density parity check (LDPC) decoding.

Assignees

• Sk Hynix Inc

Inventors

• Kim Jae-Bum

Classifications

• H03M13/1111

  Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms · CPC title

• H03M13/3715

  Adaptation to the number of estimated errors or to the channel state · CPC title

• H03M13/1108 Primary

  Hard decision decoding, e.g. bit flipping, modified or weighted bit flipping · CPC title

• G11C16/26 Primary

  Sensing or reading circuits; Data output circuits · CPC title

• G06F11/1012

  using codes or arrangements adapted for a specific type of error (G06F11/1048 takes precedence) · CPC title