Systems and methods for dynamic random access memory (DRAM) sub-channels

Patent metadata

Field	Value
Publication number	US-10468093-B2
Application number	US-201715448416-A
Country	US
Kind code	B2
Filing date	Mar 2, 2017
Priority date	Mar 3, 2016
Publication date	Nov 5, 2019
Grant date	Nov 5, 2019

Abstract

A method and system for a DRAM having a first bank that includes a first sub-array (SA) and a second SA. The first SA includes a first storage unit coupled to a first row-buffer in a first sub-channel (FSC) and a second storage unit in a second sub-channel (SSC). The second SA includes a third storage unit and a fourth storage unit coupled to a second row-buffer. The first SA is associated with a first row address (RA) and the FSC is associated with a first column address (CA) stored in the FSC. The second SA is associated with a second RA and the SSC is associated with a second CA stored in the SSC. The first and second CAs are used to select portions of data from the first and second row-buffers, respectively, for output to a data bus.

First claim

What is claimed is:

1. A dynamic random access memory (DRAM), comprising:
control logic for generating row addresses and column addresses, wherein the control logic provides a first row address to a first sub-array and a second row address to a second sub-array; and
a first bank that is coupled to the control logic, the first bank comprising:
the first sub-array including a first storage unit coupled to a first row-buffer in a first sub-channel and a second storage unit in a second sub-channel, wherein the first sub-array receives the first row address, and wherein a first column address is stored in the first sub-channel and used to select a first portion of data from the first row-buffer for output to a data bus; and
the second sub-array including a third storage unit in the first sub-channel and a fourth storage unit coupled to a second row-buffer in the second sub-channel, wherein the second sub-array receives the second row address, and wherein a second column address is stored in the second sub-channel and used to select a second portion of data from the second row-buffer for output to the data bus.

2. The DRAM of claim 1 , wherein the first portion and the second portion are output to the data bus simultaneously.

3. The DRAM of claim 1 , further comprising:
first segment select signals configured to individually enable the first sub-channel and the second sub-channel in at least one of the first storage unit and the second storage unit; and
second segment select signals configured to individually enable the first sub-channel and the second sub-channel in at least one of the third storage unit and the fourth storage unit.

4. The DRAM of claim 3 , wherein the first segment select signals enable a first portion of a first row in the first storage unit and disable a second portion of the first row in the second storage unit.

5. The DRAM of claim 4 , wherein the first segment select signals also enable a third portion of the first row in a fifth storage unit in a third sub-channel.

6. The DRAM of claim 1 , wherein the second storage unit is coupled to a third row-buffer in the second sub-channel, and wherein the second column address that is stored in the second sub-channel is used to select a third portion of data from the third row-buffer for output to the data bus simultaneously with the first portion of data.

7. The DRAM of claim 1 , wherein the first column address is different than the second column address.

8. The DRAM of claim 1 , wherein bytes of input data are reordered before the input data is output to the data bus for a write operation.

9. The DRAM of claim 1 , wherein bytes of data received from the data bus are reordered before the data is output for a read operation.

10. The DRAM of claim 1 , wherein the first column address that is stored in the first sub-channel is incremented each cycle to select different portions of the first row-buffer for output to the data bus.

11. A system, comprising:
a memory controller; and
a dynamic random access memory (DRAM) coupled to the memory controller, the DRAM comprising:
control logic for generating row addresses and column addresses, wherein the control logic provides a first row address to a first subarray and a second row address to a second subarray;
a first bank that is coupled to the control logic, the first bank comprising:
the first subarray including a first storage unit coupled to a first row-buffer in a first sub-channel and a second storage unit in a second sub-channel, wherein the first subarray receives the first row address and a first column address is stored in the first sub-channel and used to select a first portion of data from the first row-buffer for output to a data bus, and
the second subarray including a third storage unit in the first sub-channel and a fourth storage unit coupled to a second row-buffer in the second sub-channel, wherein the second subarray receives the second row address and a second column address is stored in the second sub-channel and used to select a second portion of data from the second row-buffer for output to the data bus; and
a second bank that is coupled to the control logic.

12. The system of claim 11 , wherein the first portion and the second portion are output to the data bus simultaneously.

13. The system of claim 11 , further comprising:
first segment select signals configured to individually enable the first sub-channel and the second sub-channel in at least one of the first storage unit and the second storage unit; and
second segment select signals configured to individually enable the first sub-channel and the second sub-channel in at least one of the third storage unit and the fourth storage unit.

14. The system of claim 11 , wherein the memory controller is configured to reorder bytes of input data before outputting the input data to the data bus for a write operation.

15. The system of claim 11 , wherein the memory controller is configured to reorder bytes of data received from the data bus before outputting the data for a read operation.

16. A method for accessing a dynamic random access memory (DRAM), comprising:
generating row addresses and column addresses for a first bank of multiple banks within the DRAM;
providing a first row address to a first sub-array comprising a first storage unit and a second storage unit;
providing a second row address to a second sub-array comprising a third storage unit and a fourth storage unit;
providing a first column address to a first sub-channel, the first sub-channel comprising the first storage unit coupled to a first row-buffer and the third storage unit;
storing the first column address in the first sub-channel;
providing a second column address to a second sub-channel, the second sub-channel comprising the second storage unit and the fourth storage unit coupled to a second row-buffer;
storing the second column address in the second sub-channel;
selecting, based on the first column address, a first portion of data from the first row-buffer for output to a data bus; and
selecting, based on the second column address, a second portion of data from the second row-buffer for output to the data bus.

17. The method of claim 16 , wherein the first portion and the second portion are output to the data bus simultaneously.

18. The method of claim 16 , further comprising enabling a first portion of a first row in the first storage unit and disabling a second portion of the first row in the second storage unit.

19. The method of claim 16 , wherein the first column address is different than the second column address.

20. A dynamic random access memory (DRAM), comprising:
control logic for generating row addresses and column addresses; and
a first bank that is coupled to the control logic, the first bank comprising:
a first sub-array including a first storage unit coupled to a first row-buffer in a first sub-channel and a second storage unit in a second sub-channel, wherein the first sub-array receives a first row address and a first column address is stored in the first sub-channel and used to select a first portion of data from the first row-buffer for output to a data bus, the second storage unit is coupled to a third row-buffer in the second sub-channel and the second column address that is stored in the second sub-channel is used to select a third portion of data from the third row-buffer for output to the data bus simultaneously with the first portion of data, and the first portion of data and the third portion of data are accessed usi

Assignees

• Nvidia Corp

Inventors

• Chatterjee Niladrish
• O'Connor James Michael
• Johnson Daniel Robert

Classifications

• G11C11/4087

  Address decoders, e.g. bit - or word line decoders; Multiple line decoders · CPC title

• G11C11/4091 Primary

  Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating · CPC title

• G11C11/4093

  Input/output [I/O] data interface arrangements, e.g. data buffers · CPC title

• G11C8/12

  Group selection circuits, e.g. for memory block selection, chip selection, array selection · CPC title

• G11C7/1012

  Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating · CPC title