Multiple data channel memory module architecture

Patent metadata

Field	Value
Publication number	US-9449659-B2
Application number	US-201514673732-A
Country	US
Kind code	B2
Filing date	Mar 30, 2015
Priority date	Aug 20, 2007
Publication date	Sep 20, 2016
Grant date	Sep 20, 2016

Abstract

The present invention is directed generally to systems and methods which provide a memory module having multiple data channels that are independently accessible (i.e., a multi-data channel memory module). According to one embodiment, the multi-data channel memory module enables a plurality of independent sub-cache-block accesses to be serviced simultaneously. In addition, the memory architecture also supports cache-block accesses. For instance, multiple ones of the data channels may be employed for servicing a cache-block access. In one embodiment a DIMM architecture that comprises multiple data channels is provided. Each data channel supports a sub-cache-block access, and multiple ones of the data channels may be used for supporting a cache-block access. The plurality of data channels to a given DIMM may be used simultaneously to support different, independent memory access operations.

First claim

What is claimed is:

1. A memory module comprising:
memory for storing data, the memory including multiple;
multiple, independent data channels communicatively coupled to said memory;
a plurality of internal address/control channels for carrying address and control information for the multiple, independent data channels, each of the internal address/control channels for a respective plurality of data channels of the multiple, independent data channels; and
control logic configured to receive address and control information for memory access operations to be serviced b e multiple, independent data channels and configured to decode the received address and control information for a memory access operation to result in address and control information, the control logic further configured to selectively provide the address and control information to a selected internal address/control channel of the plurality of internal address/control channels and to a selected one of the respective plurality of data channels of the selected internal address/control channel based on the received address and control information for the memory access operation.

2. The memory module of claim 1 wherein said memory module comprises a dual in-line memory module (DIMM).

3. The memory module of claim 1 wherein said memory for storing data comprises at least one dynamic random access memory (DRAM).

4. The memory module of claim 3 wherein said memory comprises a plurality of separate DRAMs, and wherein each of the multiple, independent data channels provides access to a different one of the plurality of separate DRAMs.

5. The memory module of claim 1 wherein each of the multiple, independent data channels provides access to a different portion of said memory.

6. The memory module of claim 1 wherein the multiple, independent data channels are operable to carry data for independent memory access operations.

7. The memory module of claim 6 wherein the multiple, independent data channels comprise:
eight 8-bit wide data channels.

8. The memory module of claim 7 wherein, for a respective independent memory access operation being serviced by one of the eight data channels, the one data channel carries data in a burst of 8 time units, thereby carrying 8 bytes of data for servicing the respective independent memory access operation.

9. The memory module of claim 1 wherein each of the multiple, independent data channels is operable to carry a sub-cache-block of data for independent memory access operations.

10. The memory module of claim 9 wherein, over a time period for carrying a cache-block of data, the multiple, independent data channels each carry a sub-cache-block of data.

11. The memory module of claim 10 wherein each of the multiple, independent data channels carries said sub-cache-block of data for servicing a different, independent memory access operation.

12. The memory module of claim 11 wherein the time period for carrying said cache-block of data comprises an 8 time unit burst of 64-bytes of data.

13. The memory module of claim 12 wherein the 8 time unit burst comprises either 8 clock cycles or 8 clock phases.

14. The memory module of claim 12 wherein during said 8 time unit burst said multiple, independent data channels each carries 8-bytes of data for a different one of eight independent memory access operations.

15. The memory module of claim 1 wherein the control logic receives the address and control information from an external memory controller via an address/control channel.

16. The memory module of claim 1 wherein the received address and control information comprises row select and column access commands encoded into a single command.

17. The memory module of claim 16 wherein dual data rate (DDR) signaling is employed for the received address and control information.

18. The memory module of claim 1 wherein the plurality of internal address/control channels comprise four independent internal address/control channels.

19. The memory module of claim 18 wherein the multiple, independent data channels comprise eight independent data channels, and wherein each of the four independent internal address/control channels carries address and control information for two of the eight independent data channels.

Assignees

• Micron Technology Inc

Inventors

• Brewer Tony M
• Andrewartha J Michael
• O'Leary William D
• Dugan Michael K

Classifications

• G06F12/0607 Primary

  Interleaved addressing · CPC title

• G06F12/04

  Addressing variable-length words or parts of words · CPC title

• G11C7/1072 Primary

  for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories · CPC title

• G06F2212/283

  Plural cache memories · CPC title

• G06F12/0811 Primary

  with multilevel cache hierarchies · CPC title