Dual metal-insulator-semiconductor contact structure and formulation method

US9735111B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9735111-B2
Application numberUS-201514862894-A
CountryUS
Kind codeB2
Filing dateSep 23, 2015
Priority dateSep 23, 2015
Publication dateAug 15, 2017
Grant dateAug 15, 2017

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  1. Title

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  2. Abstract

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method of making a semiconductor device includes forming a first source/drain trench and a second source/drain trench over a first and second source/drain region, respectively; forming a first silicon dioxide layer in the first source/drain trench and a second silicon dioxide layer in the second source/drain trench; forming a first source/drain contact over the first source/drain region, the first source/drain contact including a first tri-layer contact disposed between the first silicon dioxide layer and a first conductive material; and forming a second source/drain contact over the second source/drain region, the second source/drain contact including a second tri-layer contact disposed between the second silicon dioxide layer and a second conductive material; wherein the first tri-layer contact includes a first metal oxide layer in contact with the first silicon dioxide layer, and the second tri-layer contact includes a second metal oxide layer in contact with the second silicon dioxide layer.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of making a semiconductor device, the method comprising: forming a first source/drain trench over a first source/drain region in a first transistor and a second source/drain trench over a second source/drain region in a second transistor; forming a first silicon dioxide layer in the first source/drain trench and a second silicon dioxide layer in the second source/drain trench; forming a first source/drain contact over the first source/drain region, the first source/drain contact comprising a first tri-layer contact disposed between the first silicon dioxide layer and a first conductive material; and forming a second source/drain contact over the second source/drain region, the second source/drain contact comprising a second tri-layer contact disposed between the second silicon dioxide layer and a second conductive material; wherein the first tri-layer contact comprises a first metal oxide layer in contact with the first silicon dioxide layer, and the second tri-layer contact comprises a second metal oxide layer in contact with the second silicon dioxide layer. 2. The method of claim 1 , wherein the first metal oxide layer is different than the second metal oxide layer. 3. The method of claim 1 , wherein the first metal oxide layer is aluminum oxide, and the second metal oxide layer is lanthanum oxide. 4. The method of claim 1 , further comprising disposing a conductive liner layer between the first silicon dioxide layer and the first tri-layer contact or the second silicon dioxide layer and the second tri-layer contact. 5. The method of claim 1 , wherein the conductive liner layer comprises titanium nitride. 6. The method of claim 1 , wherein the first tri-layer contact further comprises a layer of titanium disposed over the first metal oxide layer. 7. The method of claim 6 , wherein the first tri-layer contact further comprises a layer of titanium nitride disposed between the layer of titanium and the first conductive material. 8. The method of claim 1 , wherein the second tri-layer contact further comprises a layer of titanium disposed over the second metal oxide layer. 9. The method of claim 1 , wherein the second tri-layer contact further comprises a layer of titanium disposed over the second metal oxide layer and a layer of titanium nitride disposed between the layer of titanium and the second conductive material. 10. A method of making a semiconductor device, the method comprising: forming a first source/drain trench over a first source/drain region in a first transistor and a second source/drain trench over a second source/drain region in a second transistor; forming a first silicon dioxide layer in the first source/drain trench and a second silicon dioxide layer in the second source/drain trench; disposing a first metal oxide layer onto the first silicon dioxide layer and along a first sidewall of the first source/drain trench and over the second silicon dioxide layer and along a sidewall of the second source/drain trench; removing the first metal oxide layer from the second source/drain trench; disposing a second metal oxide layer followed by a conductive liner layer over the first metal oxide layer within the first source/drain trench and directly onto the second silicon dioxide layer and along the sidewall of the second source/drain trench; removing by a selective process, the second metal oxide layer and the conductive liner layer from the first source/drain trench; and filling the first source/drain trench and the second source/drain trench with a conductive material. 11. The method of claim 10 , further comprising disposing a conductive layer over the first silicon dioxide layer within the first source/drain trench and removing the conductive layer from the first source/drain trench before disposing the first metal oxide layer. 12. The method of claim 10 , further comprising disposing a conductive layer over the second silicon dioxide layer within the second source/drain trench before disposing the first metal oxide layer, and then removing the conductive layer along with the first metal oxide layer. 13. The method of claim 10 , further comprising disposing a titanium layer and a titanium nitride layer between the conductive material and the first metal oxide layer within the first source/drain trench and between the conductive material and the second metal oxide layer within the second source/drain trench. 14. The method of claim 10 , further comprising removing the conductive liner layer before filling the first source/drain trench and the second source/drain trench with the conductive material. 15. The method of claim 10 , wherein the first metal oxide layer comprises aluminum oxide, and the second metal oxide layer comprises lanthanum oxide. 16. A method of making a semiconductor device, the method comprising: forming a first source/drain trench over a first source/drain in a first transistor and a second source/drain trench over a second source/drain in a second transistor; forming a first silicon dioxide layer in the first source/drain trench and a second silicon dioxide layer in the second source/drain trench, the first silicon dioxide layer directly contacting a top portion of the first source/drain, and the second silicon dioxide layer directly contacting a top portion of the second source/drain; forming a first source/drain contact over the first source/drain, the first source/drain contact comprising a first tri-layer liner disposed between the first silicon dioxide layer and a first conductive material, the first tri-layer liner comprising a first metal oxide layer in contact with the first silicon dioxide layer; and forming a second source/drain contact over the second source/drain, the second source/drain contact comprising a second tri-layer liner disposed between the second silicon dioxide layer and a second conductive material, the second tri-layer contact comprising a second metal oxide layer in contact with the second silicon dioxide layer; wherein the first metal oxide layer is different than the second metal oxide layer.

Assignees

Inventors

Classifications

  • the material containing at least one rare earth metal element, e.g. oxides of lanthanides, scandium or yttrium · CPC title

  • the material containing aluminium, e.g. Al2O3 · CPC title

  • the material being a silicon oxide, e.g. SiO2 · CPC title

  • using a gas or vapour · CPC title

  • by forming openings in the dielectric parts · CPC title

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What does patent US9735111B2 cover?
A method of making a semiconductor device includes forming a first source/drain trench and a second source/drain trench over a first and second source/drain region, respectively; forming a first silicon dioxide layer in the first source/drain trench and a second silicon dioxide layer in the second source/drain trench; forming a first source/drain contact over the first source/drain region, the …
Who is the assignee on this patent?
IBM, Globalfoundries Inc, Globalfoundries Inc
What technology area does this patent fall under?
Primary CPC classification H10W20/20. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 15 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).