Intergrated circuit devices including an interfacial dipole layer

Patent metadata

Field	Value
Publication number	US-9620612-B2
Application number	US-201514625974-A
Country	US
Kind code	B2
Filing date	Feb 19, 2015
Priority date	Feb 19, 2015
Publication date	Apr 11, 2017
Grant date	Apr 11, 2017

Abstract

An integrated circuit device includes a first transistor structure formed in a memory region (e.g., an embedded memory region) of a die. The first transistor structure includes a substrate (e.g., a planar substrate of a planar FET or a fin of a FinFET) and a first gate. The first gate includes a dipole layer proximate to the substrate and a barrier layer proximate to the dipole layer. The integrated circuit device further includes a second transistor structure formed in a logic device region of the die. The second transistor structure includes a second gate that includes an interface layer, a dielectric layer, and a cap layer. The dielectric layer is formed between the cap layer and the interface layer.

First claim

What is claimed is:

1. An integrated circuit device, comprising:
a first transistor structure in a memory region of a die, the first transistor structure having a substrate and a first gate, the first gate including a dipole layer proximate to the substrate and a barrier layer proximate to the dipole layer; and
a second transistor structure in a logic device region of the die, the second transistor structure having a second gate, the second gate including an interface layer, a dielectric layer, and a cap layer, the dielectric layer between the cap layer and the interface layer.

2. The integrated circuit device of claim 1 , wherein the barrier layer is on the dipole layer and on the cap layer.

3. The integrated circuit device of claim 1 , wherein the dielectric layer includes hafnium oxide (HfO 2 ), the dipole layer includes hafnium silicon oxide (HfSiO 4 ), or both.

4. The integrated circuit device of claim 1 , wherein the first transistor structure comprises a first field effect transistor (FET), the substrate includes a substrate of the first FET, and the second transistor structure comprises a second FET.

5. The integrated circuit device of claim 4 , wherein the interface layer is proximate to a second substrate of the second FET.

6. The integrated circuit device of claim 1 , wherein a gate stack of the first gate includes:
a metal layer proximate to the barrier layer;
a second barrier layer proximate to the metal layer; and
a fill metal layer proximate to the second barrier layer.

7. The integrated circuit device of claim 6 , wherein a gate stack of the second gate includes:
the interface layer proximate to a second substrate;
the dielectric layer proximate to the interface layer;
the cap layer proximate to the dielectric layer;
the barrier layer proximate to the cap layer;
the metal layer proximate to the barrier layer;
the second barrier layer proximate to the metal layer; and
the fill metal layer proximate to the second barrier layer.

8. An integrated circuit device comprising:
means for storing one or more bits formed in a memory region of a die, the means for storing including a first gate that includes a dipole layer; and
means for performing a logical function formed in a logic device region of the die, the means for performing including a second gate, the second gate including an interface layer, a dielectric layer, and a cap layer, the dielectric layer proximate to the interface layer and between the cap layer and the interface layer.

9. The integrated circuit device of claim 8 , wherein a barrier layer is on the dipole layer and on the cap layer.

10. The integrated circuit device of claim 8 , wherein the dielectric layer includes hafnium oxide (HfO 2 ), the dipole layer includes hafnium silicon oxide (HfSiO 4 ), or both.

11. The integrated circuit device of claim 8 , wherein a gate stack of the first gate includes:
a metal layer proximate to a barrier layer;
a second barrier layer proximate to the metal layer; and
a fill metal layer proximate to the second barrier layer.

12. The integrated circuit device of claim 11 , wherein a gate stack of the second gate includes:
the interface layer proximate to a second substrate;
the dielectric layer proximate to the interface layer;
the cap layer proximate to the dielectric layer;
the barrier layer proximate to the cap layer;
the metal layer proximate to the barrier layer;
the second barrier layer proximate to the metal layer; and
the fill metal layer proximate to the second barrier layer.

Assignees

• Qualcomm Inc

Inventors

• Xu Jeffrey Junhao
• Li Xia

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P14/69394

  the material containing titanium, e.g. TiO2 · CPC title

• H10P14/69392

  the material containing hafnium, e.g. HfO2 · CPC title

• H10P14/693

  the material containing hafnium, e.g. HfSiOx or HfSiON · CPC title

• H10D64/0134

  with a treatment, e.g. annealing, after the formation of the insulator and before the formation of the conductor · CPC title