Methods for SiO2 filling of fine recessed features and selective SiO2 deposition on catalytic surfaces

Patent metadata

Field	Value
Publication number	US-10049913-B2
Application number	US-201715484972-A
Country	US
Kind code	B2
Filing date	Apr 11, 2017
Priority date	Apr 12, 2016
Publication date	Aug 14, 2018
Grant date	Aug 14, 2018

Abstract

Methods for void-free SiO 2 filling of fine recessed features and selective SiO 2 deposition on catalytic surfaces are described. According to one embodiment, the method includes providing a substrate containing recessed features, coating surfaces of the recessed features with a metal-containing catalyst layer, in the absence of any oxidizing and hydrolyzing agent, exposing the substrate at a substrate temperature of approximately 150° C. or less, to a process gas containing a silanol gas to deposit a conformal SiO 2 film in the recessed features, and repeating the coating and exposing at least once to increase the thickness of the conformal SiO 2 film until the recessed features are filled with SiO 2 material that is void-free and seamless in the recessed features. In one example, the recessed features filled with SiO 2 material form shallow trench isolation (STI) structures in a semiconductor device.

First claim

What is claimed is:

1. A substrate processing method, the method comprising:
providing a substrate containing recessed features;
coating surfaces of the recessed features with a metal-containing catalyst layer;
in the absence of any oxidizing and hydrolyzing agent, exposing the substrate at a substrate temperature of approximately 150° C. or less, to a process gas containing a silanol gas to deposit a conformal SiO 2 film in the recessed features; and
repeating the coating and exposing at least once to increase the thickness of the conformal SiO 2 film until the recessed features are filled with SiO 2 material that is void-free and seamless in the recessed features, wherein the coating and exposing are performed a plurality of times, the first time the sidewalls of the recessed features are coated with Al 2 O 3 and thereafter the sidewalls are coated with trimethylaluminum (AlMe 3 ) each time the coating is repeated.

2. The method of claim 1 , wherein the silanol gas is selected from the group consisting of tris(tert-pentoxy) silanol, tris(tert-butoxy) silanol, and bis(tert-butoxy)(isopropoxy) silanol.

3. The method of claim 1 , wherein the metal-containing catalyst layer contains aluminum, titanium, or a combination thereof.

4. The method of claim 3 , wherein the metal-containing catalyst layer is selected from the group consisting of Al, Al 2 O 3 , AlN, AlON, an Al-containing precursor, Al-alloys, CuAl, TiAlN, TaAlN, Ti, TiAlC, TiO 2 , TiON, TiN, a Ti-containing precursor, Ti-alloys, and combinations thereof.

5. The method of claim 1 , wherein the coating includes exposing the substrate to trimethylaluminum (AlMe 3 ) gas.

6. The method of claim 1 , wherein the substrate temperature is approximately 100° C. or less, during the exposing.

7. The method of claim 1 , wherein the process gas consists of a silanol gas and an inert gas.

8. The method of claim 1 , wherein the recessed features filled with SiO 2 material form shallow trench isolation (STI) structures in a semiconductor device.

9. The method of claim 1 , further comprising
removing excess SiO 2 from above the recessed feature in a planarizing process.

10. The method of claim 9 , wherein the removing is performed using chemical-mechanical planarization (CMP).

11. A substrate processing method, the method comprising:
providing a substrate containing recessed features;
coating surfaces of the recessed features with a metal-containing catalyst layer;
in the absence of any oxidizing and hydrolyzing agent, exposing the substrate at a substrate temperature of approximately 150° C. or less, to a process gas containing a silanol gas to deposit a conformal SiO 2 film in the recessed features; and
repeating the coating and exposing at least once to increase the thickness of the conformal SiO 2 film until the recessed features are filled with SiO 2 material that is void-free and seamless in the recessed features, wherein the coating and exposing are performed a plurality of times, the first time the sidewalls are coated with HfO 2 , and Al 2 O 3 on the HfO 2 , and thereafter the sidewalls are coated with trimethylaluminum (AlMe 3 ) each time the coating is repeated.

12. A substrate processing method, the method comprising:
providing a substrate containing a first material containing a first surface and a second material containing a second surface, where the second surface contains a metal-containing catalyst layer; and
in the absence of any oxidizing and hydrolyzing agent, exposing the substrate at a substrate temperature of approximately 150° C. or less, to a process gas containing a silanol gas to selectively deposit a SiO 2 film on the second surface, but not on the first surface.

13. The method of claim 12 , wherein the silanol gas is selected from the group consisting of tris(tert-pentoxy) silanol, tris(tert-butoxy) silanol, and bis(tert-butoxy)(isopropoxy) silanol.

14. The method of claim 12 , wherein the metal-containing catalyst layer contains aluminum, titanium, or a combination thereof.

15. The method of claim 12 , wherein the metal-containing catalyst layer is selected from the group consisting of Al, Al 2 O 3 , AlN, AlON, an Al-containing precursor, Al-alloys, CuAl, TiAlN, TaAlN, Ti, TiAlC, TiO 2 , TiON, TiN, a Ti-containing precursor, Ti-alloys, and combinations thereof.

16. The method of claim 12 , wherein the first material is selected from the group consisting of silicon, germanium, silicon germanium, a dielectric material, a metal, and a metal-containing material.

17. The method of claim 16 , wherein the dielectric material is selected from the group consisting of SiO 2 , SiON, SiN, a high-k material, a low-k material, and an ultra-low-k material.

18. The method of claim 12 , wherein the substrate temperature is approximately 100° C. or less, during the exposing.

19. The method of claim 12 , wherein the process gas consists of a silanol gas and an inert gas.

20. The method of claim 12 , wherein the first surface does not contain the metal-containing catalyst layer.

Assignees

• Tokyo Electron Ltd

Inventors

• Tapily Kandabara N

Classifications

• C23C16/402

  Silicon dioxide · CPC title

• H10P14/69392

  the material containing hafnium, e.g. HfO2 · CPC title

• H10P14/69391

  the material containing aluminium, e.g. Al2O3 · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10P14/6686

  the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane · CPC title