Integrated two-terminal device with logic device for embedded application

Patent metadata

Field	Value
Publication number	US-10446607-B2
Application number	US-201615393200-A
Country	US
Kind code	B2
Filing date	Dec 28, 2016
Priority date	Dec 28, 2016
Publication date	Oct 15, 2019
Grant date	Oct 15, 2019

Abstract

Devices and methods of forming a device are disclosed. The method includes providing a substrate and a first upper dielectric layer over first and second regions of the substrate. The first upper dielectric layer includes a first upper interconnect level with a plurality of metal lines in the regions. A two-terminal device element which includes a device layer coupled in between first and second terminals is formed over the first upper dielectric layer in the second region. The first terminal contacts the metal line in the first upper interconnect level of the second region and the second terminal is formed on the device layer. An encapsulation liner covers at least exposed side surfaces of the device layer of the two-terminal device element. A dielectric layer which includes a second upper interconnect level with dual damascene interconnects is provided in the regions. The dual damascene interconnect in the first region is coupled to the metal line in the first region and the dual damascene interconnect in the second region is coupled to the two-terminal device element.

First claim

What is claimed is:

1. A method of forming a device, comprising:
providing a substrate defined with at least first and second regions;
providing a first dielectric layer over the first and second regions of the substrate, wherein the first dielectric layer comprises a first interconnect level;
forming an etch stop layer over the first region and the second region, wherein the etch stop layer covers the first dielectric layer;
patterning the etch stop layer to form a trench opening in the second region, wherein the trench opening extends from a top surface of the etch stop layer to a top surface of a metal line of the first dielectric layer in the second region;
forming a bottom electrode in the second region over the first dielectric layer, wherein the bottom electrode is in direct contact with the metal line in the first interconnect level of the second region;
forming a device layer on the bottom electrode;
forming a top electrode layer on a top surface of the device layer;
patterning the device layer and the top electrode layer to respectively form a device stack of a two-terminal device element and a top electrode, wherein the two-terminal device element is disposed over the bottom electrode, and the bottom electrode extends beyond sidewalls of the device stack;
forming an encapsulation liner over the first region and the second region, wherein the encapsulation liner covers exposed side surfaces of the device layer of the two-terminal device element; and
providing a second dielectric layer over the first and second regions and covering the first dielectric layer, wherein the second dielectric layer comprises a second interconnect level with a first dual damascene interconnect in the first region and a second dual damascene interconnect in the second region, the first dual damascene interconnect in the first region is formed over and is coupled to the metal line of the first dielectric layer in the first region, and the second dual damascene interconnect in the second region is coupled to the top electrode of the two-terminal device element.

2. The method of claim 1 wherein the encapsulation liner covers the top electrode of the two-terminal device element around the second dual damascene interconnect in the second region.

3. The method of claim 1 wherein the first region is a logic region for accommodating at least one logic component, the second region is a memory cell region for accommodating a magnetic random access memory (MRAM) cell, the two-terminal device element comprises a storage element of the MRAM cell, and the device layer comprises a magnetic tunneling junction element.

4. The method of claim 1 wherein the first and second dielectric layers comprise low-k dielectric layers.

5. The method of claim 1 comprising:
forming a bottom electrode layer in the second region over the first dielectric layer and filling the trench opening; and
performing a planarization process to remove excess bottom electrode layer to define the bottom electrode in the second region.

6. The method of claim 1 wherein the device layer includes magnetic tunneling junction layers, the two-terminal device element is a magnetic tunneling junction element, and the device stack is a magnetic tunneling junction stack.

7. The method of claim 1 wherein patterning the device layer and the top electrode layer to respectively form the device stack of the two-terminal device element and the top electrode comprises:
providing a mask over the top electrode layer; and
performing an etch process to remove exposed portions of the top electrode layer and the device layer not protected by the mask in the first and second regions.

8. A method of forming a device, comprising:
providing a substrate defined with at least first and second regions;
providing a first dielectric layer over the first and second regions of the substrate, wherein the first dielectric layer comprises a first interconnect level;
forming a bottom electrode in the second region over the first dielectric layer, wherein the bottom electrode in direct contact with a metal line in the first interconnect level of the second region;
forming a device layer on the bottom electrode;
forming a top electrode layer on a top surface of the device layer;
patterning the device layer and the top electrode layer to respectively form a device stack of a two-terminal device element and a top electrode, wherein the two-terminal device element is disposed over the bottom electrode;
providing a second dielectric layer over the first and second regions and covering the first dielectric layer, wherein the second dielectric layer comprises a second interconnect level with a first dual damascene interconnect in the first region and a second dual damascene interconnect in the second region, the first dual damascene interconnect in the first region is formed over and is coupled to the metal line of the first dielectric layer in the first region, and the second dual damascene interconnect in the second region is coupled to the top electrode of the two-terminal device element;
forming an encapsulation liner over the first region and the second region, wherein the encapsulation liner lines the second dielectric layer, the bottom electrode layer, and sides and a top of the two-terminal device element; and
removing portions of the encapsulation liner over the first region and the second region while leaving the encapsulation liner lining the sides and the top of the two-terminal device element.

9. The method of claim 7 wherein forming the encapsulation liner comprises:
forming a blanket encapsulation liner over the first and second regions, wherein the blanket encapsulation liner lines the second dielectric layer, the bottom electrode, and sides and a top of the device stack; and
performing an etch process, the etch process removing portions of the blanket encapsulation liner over the first region while leaving the encapsulation liner in the second region.

10. The method of claim 1 comprising:
forming a third dielectric layer covering the second dielectric layer and the encapsulation liner which covers at least exposed sides and the top surface of the two-terminal device element; and
wherein the first dual damascene interconnect and the second dual damascene interconnect are formed by performing a first dual damascene etch to define via openings in the first and second regions, wherein the first dual damascene etch stops at the etch stop layer in the first region and at the encapsulation liner on the top surface of the two-terminal device element in the second region.

11. The method of claim 10 wherein the first dual damascene interconnect and the second dual damascene interconnect are formed by further performing a second dual damascene etch, wherein the second dual damascene etch forms trenches in communication with the via openings and etches through the etch stop layer in the first region and through the encapsulation liner in the second region.

12. The method of claim 1 comprising:
forming magnetic tunneling junction layers over the first and second regions;
forming a hard mask layer over the magnetic tunneling junction layers in the first and second regions; and
patterning the hard mask layer, the top electrode layer and the magnetic tunneling junction layers using a patterned soft mask.

13. The method of claim 1 wherein the encapsulation liner covers a top surface of the two-terminal device element.

14. The method of claim 1 wherein the bottom electrode is disposed in a third dielectric layer, the third dielectric layer and the bottom electrode have coplanar top surfaces, and th

Assignees

• Globalfoundries Sg Pte Ltd
• Globalfoundaries Singapore Pte Ltd

Inventors

• Yi Wanbing
• Hsieh Curtis Chun-I
• Tan Juan Boon
• Siah Soh Yun
• Cong Hai
• See Alex
• You Young Seon
• Shum Danny Pak-Chum
• Yang Hyunwoo

Classifications

• H01L43/08

  Electricity · mapped topic

• H01L27/228

  Electricity · mapped topic

• H01L27/224 Primary

  Electricity · mapped topic

• H01L43/12

  Electricity · mapped topic

• H10B61/22 Primary

  of the field-effect transistor [FET] type · CPC title