Through via contacts with insulated substrate

Patent metadata

Field	Value
Publication number	US-9362171-B2
Application number	US-201314140553-A
Country	US
Kind code	B2
Filing date	Dec 26, 2013
Priority date	Dec 26, 2013
Publication date	Jun 7, 2016
Grant date	Jun 7, 2016

Abstract

Device and a method of forming a device are disclosed. The method includes providing a crystalline-on-insulator (COI) substrate. The COI substrate includes at least a base substrate over a buried insulator layer. Through via (TV) contacts are formed within the substrate. The TV contact extends from a top surface of the base substrate to within the buried insulator layer. Upper interconnect levels are formed over the top surface of the base substrate. A lower redistribution (RDL) is formed over a bottom surface of the base substrate. The buried insulator layer corresponds to a first RDL dielectric layer of the lower RDL and protects the sidewalls of the TV contacts.

First claim

What is claimed is:

1. A method of forming a device comprising:
providing a substrate, wherein the substrate comprises a buried oxide (BOX) layer sandwiched by a base substrate and a bottom substrate, wherein the BOX layer comprises first and second major surfaces, the first major surface contacts a bottom surface of the base substrate and the second major surface contacts a top surface of the bottom substrate;
forming a dielectric layer on the base substrate;
forming through via (TV) contacts within the substrate, wherein the TV contacts are formed in through via openings that extend from a top surface of the dielectric layer to within the BOX layer of the substrate and wherein the through via openings terminate within the BOX layer and at a distance away from the second major surface of the BOX layer which contacts the top surface of the bottom substrate;
forming upper interconnect levels on the base substrate over a top surface of the TV contacts, wherein the dielectric layer separates the upper interconnect levels from the base substrate;
providing a carrier substrate over a top surface of the upper interconnect levels; and
removing the bottom substrate and a portion of the BOX layer, wherein removing the portion of the BOX layer exposes a bottom surface of the TV contacts, and wherein the remaining BOX layer serves as a first redistribution (RDL) dielectric layer of a lower RDL of the device.

2. The method of claim 1 comprising:
forming conductive traces and a second RDL dielectric layer of the lower RDL of the device over the first RDL dielectric layer, wherein the second RDL dielectric layer contacts the first RDL dielectric layer which is the remaining BOX layer; and
coupling lower contacts to the conductive traces.

3. The method of claim 2 wherein the conductive traces and second RDL dielectric layer are formed by:
depositing a conductive layer over the first RDL dielectric layer and patterning the conductive layer to form the conductive traces; and
depositing the second RDL dielectric layer to cover the conductive traces and contacts the first RDL dielectric layer; and
patterning the second RDL dielectric layer to form openings exposing the conductive traces.

4. The method of claim 2 wherein the TV contacts extend to at least a thickness of the first RDL dielectric layer within the BOX layer.

5. The method of claim 1 wherein the bottom substrate is removed by an etch process or a backgrinding process.

6. The method of claim 2 wherein the carrier substrate is temporarily attached to the top surface of the upper interconnect levels by an adhesive layer.

7. The method of claim 6 comprising removing the carrier substrate and the adhesive after forming the lower contacts.

8. The method of claim 1 wherein:
the TV contacts comprise TV liners lining the through via openings formed within the substrate, and
the TV liners comprise a TV isolation liner and a TV seed layer.

9. The method of claim 1 wherein the carrier substrate facilitates the removal of the bottom substrate and the portion of the BOX layer.

10. The method of claim 1 wherein the portion of the BOX layer is removed by debonding, CMP, RIE or a combination thereof.

11. A method of forming a device comprising:
providing a crystalline-on-insulator (COI) substrate, wherein the COI substrate comprises at least a base substrate over a buried insulator layer, wherein the buried insulator layer comprises first and second major surfaces, the first major surface contacts a bottom surface of the base substrate and the second major surface of the buried insulator layer is spaced from the bottom surface of the base substrate by an initial thickness of the buried insulator layer;
forming through via (TV) contacts within the substrate, wherein the TV contacts are formed in through via openings that extend from at least a top surface of the base substrate to within the buried insulator layer and wherein the through via openings terminate within the buried insulator layer and at a distance away from the second major surface of the buried insulator layer;
forming upper interconnect levels over the top surface of the base substrate; and
forming a lower redistribution (RDL) over a bottom surface of the base substrate, wherein a portion of the buried insulator layer corresponds to a first RDL dielectric layer of the lower RDL and protects the sidewalls of the TV contacts.

12. The method of claim 11 wherein:
the COI substrate comprises silicon-on-insulator (SOI) substrate and further comprises a bottom substrate below the buried insulator layer having the initial thickness, wherein the second major surface of the buried insulator layer contacts a top surface of the bottom substrate; and
the TV contact extends from the top surface of the base substrate to at least a final thickness of the buried insulator layer.

13. The method of claim 12 comprising attaching a carrier substrate over the upper interconnect levels.

14. The method of claim 13 comprising processing the bottom substrate and the buried insulator layer after attaching the carrier substrate, wherein the carrier substrate facilitates the processing of the bottom substrate and the buried insulator layer.

15. The method of claim 14 wherein processing the bottom substrate and the buried insulator layer comprising:
removing the bottom substrate; and
removing a portion of the buried insulator layer from the initial thickness to the final thickness, wherein removing the portion of the buried insulator layer forms a planar surface of the buried insulator layer and exposes a bottom surface of the TV contacts.

16. The method of claim 15 wherein the planar surface of the buried insulator layer is substantially co-planar with the bottom surface of the TV contacts.

17. The method of claim 15 wherein:
the bottom substrate is removed by an etch process or a backgrinding process; and
the portion of the buried insulator layer is removed by debonding, CMP, RIE or a combination thereof.

18. The method of claim 15 comprising:
forming conductive traces and a second RDL dielectric layer of the lower RDL over and contact the first RDL dielectric layer; and
coupling lower contacts to the conductive traces.

19. The method of claim 18 comprising removing the carrier substrate after coupling the lower contacts.

20. The method of claim 13 wherein the carrier substrate is temporarily attached to the top surface of the upper interconnect levels by an adhesive layer.

Assignees

• Globalfoundries Sg Pte Ltd

Inventors

• Gong Shunqiang
• Tan Juan Boon
• Liu Wei

Classifications

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/944

  Dispositions of multiple bond pads · CPC title

• H10W72/942

  relative to underlying supporting features, e.g. bond pads, RDLs or vias · CPC title