Semiconductor integrated circuit device

Patent metadata

Field	Value
Publication number	US-10446581-B2
Application number	US-201816000967-A
Country	US
Kind code	B2
Filing date	Jun 6, 2018
Priority date	Jun 7, 2005
Publication date	Oct 15, 2019
Grant date	Oct 15, 2019

Abstract

A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.

First claim

What is claimed is:

1. A semiconductor integrated circuit device formed on one chip, comprising:
a first functional block connected to a first power supply line and a second power supply line;
a second functional block connected to the first power supply line and a third power supply line and communicating with the first functional block;
a third functional block connected to the first power supply line and a fourth power supply line and communicating with the first functional block;
a first power switch shutting down the first functional block from power supply via the second power supply line;
a second power switch shutting down the second functional block from power supply via the third power supply line;
a third power switch shutting down the third functional block from power supply via the fourth power supply line; and
a power switch controller controlling the power switches,
wherein a signal transmission between the second functional block and the third functional block is performed via the first functional block.

2. A semiconductor integrated circuit device according to claim 1 ,
wherein the first functional block comprises the power switch controller.

3. A semiconductor integrated circuit device according to claim 1 , further comprising:
a fourth functional block connected only to the first power supply line,
wherein the fourth functional block comprises the power switch controller.

4. A semiconductor integrated circuit device according to claim 1 ,
wherein the first to third functional blocks each comprise a first MISFET,
the first to third power switches and the power switch controller each comprise a second MISFET having larger gate insulation film thickness than the first MISFET, and the first to third power switches each comprise a first switch and a second switch,
wherein the power switch controller turns the first switches on first and turns the second switches on second.

5. A semiconductor integrated circuit device according to claim 4 ,
wherein the power switch controller comprises:
means to detect whether a virtual power supply line reaches a voltage level in which the functional blocks can operate; and
a sensor circuit to detect the voltage of the virtual power supply,

wherein the power switch controller controls the first switches and the second switches accordingly.

6. A semiconductor integrated circuit device according to claim 5 ,
wherein the power switch controller comprises a clock generator, and
wherein the sensor circuit comprises a dynamic comparator detecting the voltage level synchronized with a clock signal generated by the clock generator.

7. A semiconductor integrated circuit device according to claim 4 ,
wherein the power switch controller comprises a sensor circuit to detect whether the first and second switches are on or not, and
wherein the sensor circuit detects gate voltages of the second MISFETs of the first and second switches, compares the gate voltages with a predetermined voltage level, and determines whether the first and the second switches are on or not.

8. A semiconductor integrated circuit device according to claim 7 ,
wherein the power switch controller comprises a clock generator, and
wherein the sensor circuit comprises a dynamic comparator detecting the voltage level synchronized with a clock signal generated by the clock generator.

9. A semiconductor integrated circuit device according to claim 4 ,
wherein the power switch controller comprises a clock generator and a sensor circuit comprising a dynamic comparator detecting a voltage level synchronized with a clock signal generated by the clock generator.

10. A semiconductor integrated circuit device according to claim 1 ,
wherein the first functional block comprises a retaining latch circuit that saves a data stored in a latch circuit provided in one of the second to the third functional blocks.

Assignees

• Renesas Electronics Corp

Inventors

• Kanno Yusuke
• Mizuno Hiroyuki
• Yasu Yoshihiko
• Hirose Kenji
• Irita Takahiro

Classifications

• H10W72/00

  Interconnections or connectors in packages · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• G06F30/39

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• H03K3/0375

  provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails (digital storage cells each combining volatile and non-volatile storage properties G11C14/00) · CPC title

• G11C11/419

  Read-write [R-W] circuits · CPC title