Semiconductor device having a copper element and method of forming a semiconductor device having a copper element

Patent metadata

Field	Value
Publication number	US-10446469-B2
Application number	US-201615217383-A
Country	US
Kind code	B2
Filing date	Jul 22, 2016
Priority date	Dec 9, 2011
Publication date	Oct 15, 2019
Grant date	Oct 15, 2019

Abstract

A semiconductor device includes a base element and a copper element over the base element. The copper element includes a layer stack having at least two copper layers and at least one intermediate conductive layer of a material different from copper. The at least two copper layers and the at least one intermediate conductive layer are alternately stacked over each other.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a base element; and
a copper element over the base element, the copper element comprising a layer stack including at least two copper layers and at least one intermediate conductive layer of a material different from copper, the at least two copper layers and the at least one intermediate conductive layer being alternately stacked over each other, each of the at least one intermediate layer having a thickness of less than 30 nm.

2. The semiconductor device of claim 1 , wherein each of the at least two copper layers has a thickness of less than 5 μm.

3. The semiconductor device of claim 1 , further comprising a cover layer comprising at least one of NiP, NiMoP, NiPd, Ni(X)P, and Ni(X,Y)P, wherein X and Y denote further elements.

4. The semiconductor device of claim 1 , wherein the copper element is a layer, a patterned layer or a wiring.

5. A semiconductor device, comprising:
a semiconductor substrate;
components of a power device disposed in the semiconductor substrate; and
a copper element over the semiconductor substrate and electrically connected to one of the components, the copper element comprising a layer stack including at least two copper layers and at least one intermediate conductive layer of a material different from copper, the at least two copper layers and the at least one intermediate conductive layer being alternately stacked over each other, each of the at least one intermediate layer having a thickness of less than 30 nm.

6. The semiconductor device of claim 5 , wherein each of the at least two copper layers has a thickness of less than 5 μm.

7. The semiconductor device of claim 5 , further comprising a cover layer comprising at least one of NiP, NiMoP, NiPd, Ni(X)P, and Ni(X,Y)P, wherein X and Y denote further elements.

8. The semiconductor device of claim 5 , wherein the copper element is a layer, a patterned layer or a wiring.

9. The semiconductor device of claim 5 , wherein the power device is a power transistor.

10. A method of manufacturing a semiconductor device, the method comprising:
forming a copper element over a base element, by forming a layer stack including at least two copper layers and at least one intermediate conductive layer of a material different from copper, the at least two copper layers and the at least one intermediate conductive layer being alternately stacked over each other, each of the at least one intermediate layer having a thickness of less than 30 nm.

11. The method of claim 10 , wherein each of the at least two copper layers has a thickness of less than 5 μm.

12. The method of claim 10 , further comprising:
forming a cover layer comprising at least one of NiP, NiMoP, NiPd, Ni(X)P, and Ni(X,Y)P, wherein X and Y denote further elements.

13. The semiconductor device according to claim 1 , wherein the conductive intermediate layer comprises TiN.

14. The semiconductor device according to claim 5 , wherein the conductive intermediate layer comprises TiN.

15. The method of claim 10 , wherein the conductive intermediate layer comprises TiN.

Assignees

• Infineon Technologies Ag

Inventors

• Detzel Thomas
• Gross Johann
• Illing Robert
• Krug Maximilian
• Lanzerstorfer Sven Gustav
• Nelhiebel Michael
• Robl Werner
• Rogalli Michael
• Woehlert Stefan

Classifications

• H10P14/47

  Electrolytic deposition, i.e. electroplating; Electroless plating · CPC title

• H10W40/037

  Assembling together parts thereof · CPC title

• H10W20/425 Primary

  Barrier, adhesion or liner layers · CPC title

• H10W40/255 Primary

  having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates · CPC title

• H01L2924/0002

  Electricity · mapped topic