Dual-bit 3-T high density MTPROM array

Patent metadata

Field	Value
Publication number	US-9659604-B1
Application number	US-201514961484-A
Country	US
Kind code	B1
Filing date	Dec 7, 2015
Priority date	Dec 7, 2015
Publication date	May 23, 2017
Grant date	May 23, 2017

Abstract

A multi-time programmable memory (MTPM) memory cell and method of operating. Each MTPM bit cell including a first FET transistor and a second FET transistor having a first common connection, and said second FET transistor and a third FET transistor having a second common connection, said first and second connected FET transistors programmable to store a first bit value, and said second FET and said third connected FET transistors programmable to store a second bit value, wherein said first FET transistor exhibits a low threshold voltage value (LVT), said second FET transistor exhibits an elevated threshold voltage value HVT and said third FET transistor exhibits a threshold value LVT lower than HVT. The MTPM cell enables two bits of information to be stored as default bit values like an electrical fuse. To store opposite bit values, the LVT transistors are programmed such that their threshold voltage is higher than that of HVT.

First claim

What is claimed is:

1. A memory system comprising:
a multi-time programmable (MTP) bit cell array, with each multi-time programmable bit cell of the array comprising:
a first FET transistor and a second FET transistor having a first common connection, and the second FET Transistor and a third FET transistor having a second common connection, the first and second connected FET transistors programmable to store a first bit value, and the second FET transistor and the third connected FET transistors programmable to store a second bit value, wherein the first FET transistor exhibits a low threshold voltage on value (LVT), the second FET transistor exhibits an elevated threshold voltage value (HVT) and the third FET transistor exhibits a native threshold value LVT lower than HVT, wherein each MTP bit cell further comprises:
a first terminal of the first FET transistor connecting with a first bit line (True) (BLT 0 ) conductor coupled via a first column write switch device;
a second terminal of the third FET transistor connecting with a second bit line (True) (BLT 1 ) conductor coupled via a fourth column write switch device;
the second common connection formed of a second terminal of the second FET transistor and a first terminal of the third FET transistor, a third switch device for selectively connecting the second common connection to a first complement bitline conductor (BLC 0 ), and a further switch for selectively connecting the second common connection to a supply voltage source via a first source line (SL) conductor;
the first common connection formed of a second terminal of the first FET transistor and a first terminal of the second FET transistor, and a second switch device for selectively connecting the first common connection to a second complement bitline conductor (BLC 1 ), and a further switch connecting the first common connection to the supply voltage source via a second source line conductor;

a wordline conductor (WL) programmable for activating MTP bit memory cell, each of the first, second and third FET transistors of each the MTP bit memory cell including a respective gate terminal for connection with the wordline conductor (WL) element;
a sense amplifier for sensing received signals;
a multiplexor for selecting one out of many data output signals, the multiplexor responsive to control signals for activating the first switch device and third switch device to enable sensing, by the sensing amplifier, of voltage values representing a first stored information bit on the first bit line (True) conductor and first complement bit line conductor, or responsive to control signals for activating the second switch and fourth switch devices to enable sensing, by the sensing amplifier, of voltage values representing a second stored information bit on the second bit line (True) conductor and second complement bit line conductor.

2. The system of claim 1 , wherein said first bit and second bits each have a default first value to be stored in the cell, each first and second bit being separately programmable to store an opposite bit values by raising a threshold value of the LVT transistors higher than the threshold value of the HVT.

3. A method of operating a multi-time programmable (MTP) bit cell comprising:
selecting a MTP bit cell to write an initial bit value for storage at the selected bit cell, the MTP bit memory cell comprising:
a first FET transistor and a second FET transistor having a first common connection, and said second FET transistor and a third FET transistor having a second common connection, said first and second connected FET transistors programmable to store a first bit value, and said second FET and said third connected FET transistors programmable to store a second bit value, wherein said first FET transistor exhibits a low threshold voltage (LVT), said second FET transistor exhibits an elevated threshold voltage value (HVT) and said third FET transistor exhibits a low threshold value LVT lower than HVT,
wherein, a first terminal of said first FET transistor connects with a first bit line (True) conductor coupled via a first column write switch device,
a second terminal of said third FET transistor connects with a second bit line (True) conductor coupled via a fourth column write switch device;
the second common connection is formed of a connection between a second terminal of the second FET transistor and a first terminal of the third FET transistor, a third switch device for selectively connecting the second common connection to a first complement bitline conductor; and
the first common connection is formed of a connection between a second terminal of the first FET transistor and a first terminal of the second FET transistor, and a second switch device for selectively connecting the first common connection to a second complement bitline conductor; and
a further switch device for selectively connecting the second common connection to a supply voltage source via a first source line (SL) conductor, said supply voltage source for biasing said second common connection when writing to said first storage bit in said first FET transistor and second FET transistor; and

writing a first bit of information for storage at the first FET transistor and second FET transistors of said selected MTP cell by:
activating said further switch for biasing said second common connection using said SL supply voltage source; and
activating a program switch device for switching connection of a program bit voltage supply on the first bit line (True) conductor while said first column write switch device de-activated; and
applying at the first bit line (True) conductor, using the program bit voltage supply, a program voltage to said first FET transistor and second FET transistor devices for storage of a bit value thereat.

4. The method of claim 3 , wherein each of the first, second and third FET transistors of each said MTP bit memory cell includes a respective gate terminal for connection with a wordline conductor (WL) element configured for activating said cell, said selecting comprising:
asserting a signal at said WL conductor for accessing said MTP cell.

5. The method of claim 4 , wherein the MTP bit cell further comprises:
a further switch connecting the first common connection to the supply voltage source via a second source line conductor, said supply voltage source for biasing said first common connection when writing to a second bit value in said second FET transistor and said third FET transistor;
wherein the writing of the second bit value for storage at the second FET transistor and third FET transistor of said selected MTP cell comprises:
activating said further switch for biasing said first common connection using said SL supply voltage source; and
activating a program switch device for switching connection of a program bit voltage supply on the second bit line (True) conductor while said fourth column write switch device de-activated; and
applying at the second bit line (True) conductor, using the program bit voltage supply, a program voltage to said second FET transistor and third FET transistor device for storage of a bit value thereat.

6. The method of claim 5 , further comprising:
reading, using a sense amplifier, a first bit of information from said MTP bit memory cell by:
activating said first column switch device for switching connection of the stored program bit on the first bit line (True) conductor while said program switch device is deactivated; and
simultaneously activating the third switch for selectively connecting said second common connection to the first complement bitline conductor,
said sense amplifier reading a stored first programmed bit via said first bit line (True) conductor and said first complement bitline conductor.

Assignees

• Globalfoundries Inc

Inventors

• Raghavan ramesh
• Jayaraman Balaji
• Viraraghavan Janakiraman
• Kempanna Thejas
• Tummuru Rajesh Reddy
• Kirihata Toshiaki

Classifications

• G11C7/18

  Bit line organisation; Bit line lay-out · CPC title

• G11C7/062 Primary

  Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs · CPC title

• G11C7/12

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title

• G11C11/5628

  Programming or writing circuits; Data input circuits · CPC title

• G11C5/147

  Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence) · CPC title