Dynamic range reduction for analog-to-digital converters

Patent metadata

Field	Value
Publication number	US-9319062-B2
Application number	US-201414474627-A
Country	US
Kind code	B2
Filing date	Sep 2, 2014
Priority date	Sep 2, 2014
Publication date	Apr 19, 2016
Grant date	Apr 19, 2016

Abstract

In accordance with the exemplary embodiments of the invention there is at least an apparatus to perform a method including receiving by an analog-to-digital converter a signal; determining whether an in-band blocker is present in the signal; and adjusting a transfer function of the analog-to-digital converter based on whether an in-band blocker is present by configuring a loop filter of the analog-to-digital converter.

First claim

What is claimed is:

1. A method comprising:
receiving by an analog-to-digital converter a signal;
determining whether an in-band blocker is present in the signal; and
adjusting a transfer function of the analog-to-digital converter based on whether an in-band blocker is present by configuring a loop filter of the analog-to-digital converter.

2. The method of claim 1 , wherein for a case that an in-band blocker is not present in the signal the loop filter is configured to adjust a noise transfer function of the analog-to-digital converter to optimize a noise-shaping effect of the signal.

3. The method of claim 1 , wherein for a case that an in-band blocker is present the loop filter is configured to adjust a signal transfer function of the analog-to-digital converter to partially filter the in-band blocker.

4. The method of claim 1 , wherein the in-band blocker is a dominant in-band blocker.

5. The method of claim 3 , wherein in response to partially filtering the in-band blocker a dynamic response requirement of the analog-to-digital converter is reduced by 1 or more bits.

6. The method of claim 1 , wherein if the analog-to-digital converter is a discrete time converter the configuring the loop filter comprises adjusting capacitor parameters of the loop filter.

7. The method of claim 1 , wherein if the analog-to-digital converter is a continuous time delta sigma analog to digital converter the configuring the loop filter comprises adjusting resistor parameters of the loop filter.

8. The method of claim 1 , wherein the analog-to-digital converter is a delta-sigma analog-to-digital converter.

9. A non-transitory computer readable medium embodying computer program instructions, the computer program instructions executed by at least one processor to cause an apparatus to perform the method according to claim 1 .

10. An apparatus comprising:
at least one processor; and
at least one memory including computer program code, where the at least one memory and the computer program code are configured, with the at least one processor, to cause the apparatus to at least:
receive by an analog-to-digital converter a signal;
determine whether an in-band blocker is present in the signal; and
adjust a transfer function of the analog-to-digital converter based on whether an in-band blocker is present by configuring a loop filter of the analog-to-digital converter.

11. The apparatus of claim 10 , wherein for a case that an in-band blocker is not present in the signal the loop filter is configured to adjust a noise transfer function of the analog-to-digital converter to optimize a noise-shaping effect of the signal.

12. The apparatus of claim 10 , wherein for a case that an in-band blocker is present the loop filter is configured to adjust a signal transfer function of the analog-to-digital converter to partially filter the in-band blocker.

13. The apparatus of claim 10 , wherein the in-band blocker is a dominant in-band blocker.

14. The apparatus of claim 12 , wherein in response to partially filtering the in-band blocker a dynamic response requirement of the analog-to-digital converter is reduced by 1 or more bits.

15. The apparatus of claim 10 , wherein if the analog-to-digital converter is a discrete time converter the configuring the loop filter comprises adjusting capacitor parameters of the loop filter.

16. The apparatus of claim 10 , wherein if the analog-to-digital converter is a continuous time delta sigma analog to digital converter the configuring the loop filter comprises adjusting resistor parameters of the loop filter.

17. The apparatus of claim 10 , wherein the analog-to-digital converter is a delta-sigma analog-to-digital converter.

Assignees

• Nokia Corp
• Nokia Technologies Oy

Inventors

• Danneels Hans

Classifications

• H03M3/322 Primary

  Continuously compensating for, or preventing, undesired influence of physical parameters (periodically, e.g. by using stored correction values, H03M3/378) · CPC title

• H03M3/45

  with distributed feedforward inputs, i.e. with forward paths from the modulator input to more than one filter stage · CPC title

• H03M3/448

  by removing part of the zeroes, e.g. using local feedback loops · CPC title

• H03M3/368 Primary

  of noise other than the quantisation noise already being shaped inherently by delta-sigma modulators · CPC title

• H03M3/454

  with distributed feedback, i.e. with feedback paths from the quantiser output to more than one filter stage · CPC title