Method and apparatus for multi-level setback read for three dimensional crosspoint memory

Patent metadata

Field	Value
Publication number	US-10438659-B2
Application number	US-201816037255-A
Country	US
Kind code	B2
Filing date	Jul 17, 2018
Priority date	Dec 30, 2016
Publication date	Oct 8, 2019
Grant date	Oct 8, 2019

Abstract

In one embodiment, an apparatus comprises read circuitry to apply a read voltage to a three dimensional crosspoint (3DXP) memory cell; and write setback circuitry to apply a first setback pulse having a first magnitude to the 3DXP memory cell in response to the application of the read voltage, wherein applying the first setback pulse comprises bypassing a current mirror that is to limit or control a magnitude of a second setback pulse applied to the 3DXP memory cell when the current mirror is coupled to the 3DXP memory cell.

First claim

What is claimed is:

1. An apparatus comprising:
a memory cell;
a first discharge path from the memory cell to a reference voltage, including a current limiter to limit current through the memory cell to a first current; and
a second discharge path from the memory cell to the reference voltage, electrically parallel to the first discharge path, the second discharge path including a switch to selectively bypass the first discharge path including the current limiter, to increase current through the memory cell to a second current higher than the first current.

2. The apparatus of claim 1 , wherein the memory cell comprises a three dimensional crosspoint memory cell.

3. The apparatus of claim 1 , wherein the current limiter comprises a current source.

4. The apparatus of claim 1 , wherein the switch comprises multiple switches.

5. The apparatus of claim 4 , wherein the multiple switches include a first switch across inputs of a sense amplifier and a second switch in series with the first switch, from the first switch to the reference voltage.

6. The apparatus of claim 1 , wherein the switch is to selectively bypass the first discharge path responsive to a setback current control signal.

7. The apparatus of claim 1 , wherein the switch is to selectively close to bypass the first discharge path after a read pulse to setback the memory cell with the second current, and subsequently to open to limit current through the memory cell to the first current.

8. The apparatus of claim 1 , wherein the reference voltage comprises a demarcation voltage (VDM) for the memory cell.

9. The apparatus of claim 8 , wherein the first discharge path comprises a transistor from a wordline of the memory cell to a wordline demarcation voltage (WLVDM).

10. A storage device, comprising:
a nonvolatile crosspoint memory circuit, including
a memory cell;
a first discharge path from the memory cell to a reference voltage, including a current limiter to limit current through the memory cell to a first current; and
a second discharge path from the memory cell to the reference voltage, electrically parallel to the first discharge path, the second discharge path including a switch to selectively bypass the first discharge path including the current limiter, to increase current through the memory cell to a second current higher than the first current; and

a storage controller to control a read request to the memory cell, including to select between the first discharge path and the second discharge path.

11. The storage device of claim 10 , wherein the memory cell comprises a three dimensional crosspoint memory cell.

12. The storage device of claim 10 , wherein the current limiter comprises a current source.

13. The storage device of claim 10 , wherein the switch comprises multiple switches.

14. The storage device of claim 13 , wherein the multiple switches include a first switch across inputs of a sense amplifier and a second switch in series with the first switch, from the first switch to the reference voltage.

15. The storage device of claim 10 , wherein the switch is to selectively bypass the first discharge path responsive to a setback current control signal.

16. The storage device of claim 10 , wherein the switch is to selectively close to bypass the first discharge path after a read pulse to setback the memory cell with the second current, and subsequently to open to limit current through the memory cell to the first current.

17. The storage device of claim 10 , wherein the reference voltage comprises a demarcation voltage (VDM) for the memory cell.

18. The storage device of claim 17 , wherein the first discharge path comprises a transistor from a wordline of the memory cell to a wordline demarcation voltage (WLVDM).

19. The apparatus of claim 1 , wherein the current limiter comprises a current source connected in parallel with a sense amplifier to read the memory cell, wherein the switch comprises a switch device in parallel with the sense amplifier, the switch to be selectively controlled with a bypass signal.

20. The apparatus of claim 1 , wherein the current limiter comprises a current source connected in parallel with a sense amplifier to read the memory cell, wherein the switch comprises a switch device in parallel with the sense amplifier, the switch to be selectively controlled with a time delayed, inverted version of a latch signal for the sense amplifier.

21. The apparatus of claim 1 , wherein the memory cell comprises a three-dimensional crosspoint (3DXP) memory cell.

22. The apparatus of claim 1 , wherein the memory cell comprises a NAND flash memory cell or a resistance-based memory cell.

23. The storage device of claim 10 , wherein the current limiter comprises a current source connected in parallel with a sense amplifier to read the memory cell, wherein the switch comprises a switch device in parallel with the sense amplifier, the switch to be selectively controlled with a bypass signal.

24. The storage device of claim 10 , wherein the current limiter comprises a current source connected in parallel with a sense amplifier to read the memory cell, wherein the switch comprises a switch device in parallel with the sense amplifier, the switch to be selectively controlled with a time delayed, inverted version of a latch signal for the sense amplifier.

25. The storage device of claim 10 , wherein the memory cell comprises a three-dimensional crosspoint (3DXP) memory cell.

26. The storage device of claim 10 , wherein the memory cell comprises a NAND flash memory cell or a resistance-based memory cell.

Assignees

• Intel Corp

Inventors

• Srinivasan Balaji
• Chu Daniel
• Leem Lark-Hoon
• Gorman John
• Taub Mase
• Guliani Sandeep
• Pangal Kiran

Classifications

• G11C13/0069

  Writing or programming circuits or methods · CPC title

• G11C13/0061

  Timing circuits or methods · CPC title

• G11C13/0023

  Address circuits or decoders · CPC title

• G11C13/0004

  comprising amorphous/crystalline phase transition cells · CPC title

• G11C13/0033 Primary

  Disturbance prevention or evaluation; Refreshing of disturbed memory data · CPC title