Apparatuses and methods for reducing read disturb

Patent metadata

Field	Value
Publication number	US-2016111167-A1
Application number	US-201414518727-A
Country	US
Kind code	A1
Filing date	Oct 20, 2014
Priority date	Oct 20, 2014
Publication date	Apr 21, 2016
Grant date	—

Abstract

Apparatuses and methods for reducing read disturb are described herein. An example apparatus may include a first memory subblock including a first select gate drain (SGD) switch and a first select gate source (SGS) switch, a second memory subblock including a second SGD switch and a second SGS switch, and an access line associated with the first and second memory subblocks. The apparatus may include a control unit configured to enable the first and second SGD switches and the first and second SGS switches during a first portion of a read operation and to provide a first voltage on the access line during the first portion. The control unit may be configured to disable the first SGD switch and the first SGS switches during a second portion of the read operation and to provide a second voltage on the access line during the second portion.

First claim

What is claimed is:

1 . An apparatus, comprising:
a first memory subblock including a first select gate drain switch and a first select gate source switch; a second memory subblock including a second select gate drain switch and a second select gate source switch; an access line associated with the first memory subblock and the second memory subblock; and a control unit coupled to the first and second select gate drain switches and the first and second select gate source switches, the control unit configured to enable the first and second select gate drain switches and the first and second select gate source switches during a first portion of a read operation and to provide a first voltage on the access line during the first portion of the read operation, the control unit further configured to disable the first select gate drain switch and the first select gate source switch during a second portion of the read operation and to provide a second voltage on the access line during the second portion of the read operation.

2 . The apparatus of claim 1 , wherein the second voltage is greater than the first voltage.

3 . The apparatus of claim 1 , wherein the access line is a first access line, the apparatus further comprising:
a second access line, the control unit configured to provide a third voltage on the second access line during at least one of the first or second portions of the read operation, the third voltage lower than the first voltage.

4 . The apparatus of claim 1 , wherein the first memory subblock is an unselected memory subblock and the second memory subblock is a selected memory subblock during the read operation.

5 . The apparatus of claim 1 , wherein the first and second memory subblocks share a same set of signal lines.

6 . The apparatus of claim 1 , wherein the first memory subblock is associated with a first select gate source line and the second memory subblock is associated with a second select gate source line.

7 . The apparatus of claim 1 , wherein the apparatus is included in a three-dimensional memory array.

8 . An apparatus, comprising:
a plurality of memory subblocks including a plurality of select gate source switches; an access line associated with each of the plurality of subblocks; and a control unit coupled to each of a plurality of memory subblocks, the control unit configured to enable select gate source switches of the plurality of memory subblocks and to provide a control signal to each of the plurality of memory subblocks at a first voltage using the access line, the control unit further configured to selectively disable each of the plurality of select gate source switches of the plurality of memory subblocks responsive, at least in part, to providing the control signal at the first voltage and to provide the control signal to each of the plurality of memory subblocks at a second voltage using the access line responsive, at least in part, to selectively disabling each of the plurality of select gate source switches of the plurality of memory subblocks.

9 . The apparatus of claim 8 , wherein the second voltage is greater than the first voltage.

10 . The apparatus of claim 8 , wherein the control unit is configured to enable select gate source switches of the plurality of memory subblocks and to provide the control signal to each of the plurality of memory subblocks at the first voltage during a read operation.

11 . The apparatus of claim 8 , wherein the control unit is configured to selectively provide an inactive control signal to each of the plurality of select gate source switches of the plurality of memory subblocks to selectively disable each of the plurality of select gate source switches of the plurality of memory subblocks.

12 . The apparatus of claim 8 , wherein the apparatus is included in a memory.

13 . A method, comprising:
enabling a select gate source switch of a first memory subblock and a second gate source switch of a second memory subblock; providing a control signal on an access line associated with the first memory subblock and the second memory subblock; increasing a voltage of the control signal to a first voltage; disabling the select gate source switch of the first memory subblock; and increasing the voltage of the control signal from the first voltage to a second voltage.

14 . The method of claim 13 , wherein disabling the select gate source switch of the first memory subblock comprises:
providing an inactive control signal on a select gate source line associated with the first memory subblock.

15 . The method of claim 13 , wherein increasing the voltage of the control signal from the first voltage to a second voltage comprises:
causing a plurality of memory cells of the first memory subblock and a plurality of memory cells of the second memory subblock to be conductive.

16 . The method of claim 13 , wherein increasing a voltage of the control signal to a first voltage:
holding a magnitude of a channel voltage at a voltage.

17 . The method of claim 13 , further comprising:
enabling a select gate drain switch of the first memory subblock and a second gate drain switch of the second memory subblock; and before increasing the voltage of the control signal from the first voltage to a second voltage, disabling the select gate drain switch of the first memory subblock.

18 . A method, comprising:
providing a control signal on each of a plurality of access lines during a read operation; increasing the voltage of the control signal while each of a plurality of select gate drain switches and each of a plurality of select gate source switches are enabled; selectively disabling each of the plurality of select gate drain switches and each of the plurality of select gate source switches; and increasing the voltage of the control signal.

19 . The method of claim 18 , wherein selectively disabling each of the plurality of select gate drain switches and each of the plurality of select gate source switches comprises:
disabling each select gate drain switch associated with an unselected subblock during the read operation; and selectively disabling each select gate source switch associated with an unselected memory subblock during the read operation.

20 . The method of claim 19 , wherein selectively disabling each select gate source switch associated with an unselected memory subblock comprises:
disabling each select gate source switch associated with an inactive select gate source line.

21 . The method of claim 18 , wherein increasing the voltage of the control signal while each of a plurality of select gate drain switches and each of a plurality of select gate source switches are enabled comprises:
holding a channel voltage at a magnitude.

22 . A method, comprising:
providing an active control signal on first and second select gate source lines, the first select gate source line associated with a first plurality of subblocks and the second select gate source line associated with a second plurality of subblocks; providing a control signal at a first voltage to each of the first and second pluralities of subblocks; providing an inactive control signal on the first select gate source line; and providing a control signal at a second voltage to each of the first and second pluralities of subblocks, the second voltage greater than the first voltage.

23 . The method of claim 22 , wherein providing an inactive control signal on the first

Assignees

• Micron Technology Inc

Inventors

• Pan Feng
• Ghodsi Ramin
• Tang Qiang

Classifications

• G11C16/26 Primary

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/24

  Bit-line control circuits · CPC title

• G11C16/3427 Primary

  Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title