Integrated setback read with reduced snapback disturb

Patent metadata

Field	Value
Publication number	US-9437293-B1
Application number	US-201514671471-A
Country	US
Kind code	B1
Filing date	Mar 27, 2015
Priority date	Mar 27, 2015
Publication date	Sep 6, 2016
Grant date	Sep 6, 2016

Abstract

Embodiments of the present disclosure describe read and write operations in phase change memory to reduce snapback disturb. In an embodiment, an apparatus includes read circuitry to apply a read voltage to a phase change memory (PCM) cell, setback circuitry to apply a setback pulse to the PCM cell in response to the application of the read voltage, wherein the setback pulse is a shorter set pulse performed for a first period of time that is shorter than a second period of time for a regular set pulse that is configured to transition the PCM cell from an amorphous state to a crystalline state, sense circuitry to sense, concurrently with application of the setback pulse, whether the PCM cell is in the amorphous state or the crystalline state. Other embodiments may be described and/or claimed.

First claim

What is claimed is:

1. An apparatus comprising:
read circuitry, to apply a read voltage to a phase change memory (PCM) cell;
setback circuitry coupled to the read circuitry, to apply a setback pulse to the PCM cell in response to the application of the read voltage, wherein the setback pulse is a shorter set pulse performed for a first period of time that is shorter than a second period of time for a regular set pulse that is to transition the PCM cell from an amorphous state to a crystalline state; and
sense circuitry coupled to the setback circuitry, to sense, concurrently with application of the setback pulse, whether the PCM cell is in the amorphous state or the crystalline state.

2. The apparatus of claim 1 , wherein the first period of time is 1/100 th of the second period of time or greater.

3. The apparatus of claim 2 , wherein the first period of time is 1/20 th of the second period of time or less.

4. The apparatus of claim 1 , wherein the setback circuitry is to apply the setback pulse to the PCM cell based on the PCM cell turning on in response to application of the read voltage.

5. The apparatus of claim 4 , wherein the PCM cell is in the crystalline state and wherein the sense circuitry is to sense whether the PCM cell is in the amorphous state or the crystalline state subsequent to or simultaneously with the PCM cell turning on in response to application of the read voltage and prior to the PCM cell turning off.

6. The apparatus of claim 1 , wherein the PCM cell is in the crystalline state and wherein the setback circuitry is to perform the setback pulse subsequent to or simultaneously with the PCM cell turning on in response to application of the read voltage and prior to the PCM cell turning off.

7. The apparatus of claim 1 , further comprising:
current-limiting circuitry to limit or control a setback current through the PCM cell when the setback pulse is performed.

8. The apparatus of claim 1 , further comprising:
a transistor coupled with the PCM cell to reduce or isolate capacitance discharge from disturbing the PCM cell when the PCM cell turns on in response to application of the read voltage.

9. A method comprising:
applying a read voltage to a phase change memory (PCM) cell;
applying a setback pulse to the PCM cell in response to the application of the read voltage, wherein the setback pulse is a shorter set pulse performed for a first period of time that is shorter than a second period of time for a regular set pulse that is to transition the PCM cell from an amorphous state to a crystalline state; and
sensing, concurrently with applying the setback pulse, whether the PCM cell is in the amorphous state or the crystalline state.

10. The method of claim 9 , wherein the first period of time is 1/100 th of the second period of time or greater.

11. The method of claim 10 , wherein the first period of time is 1/20 th of the second period of time or less.

12. The method of claim 9 , wherein applying the setback pulse to the PCM cell is performed in response to the PCM cell turning on based on application of the read voltage.

13. The method of claim 12 , wherein the PCM cell is in the crystalline state and wherein the sensing is performed subsequent to or simultaneously with the PCM cell turning on in response to application of the read voltage and prior to the PCM cell turning off.

14. The method of claim 9 , wherein the PCM cell is in the crystalline state and wherein the setback pulse is applied subsequent to or simultaneously with the PCM cell turning on in response to application of the read voltage and prior to the PCM cell turning off.

15. The method of claim 9 , further comprising:
limiting or controlling a setback current through the PCM cell when the setback pulse is performed.

16. A non-transitory computer-readable medium having instructions stored thereon, the instructions when executed by a processor cause circuitry to:
apply a read voltage to a phase change memory (PCM) cell;
apply a setback pulse to the PCM cell in response to the application of the read voltage, wherein the setback pulse is a shorter set pulse performed for a first period of time that is shorter than a second period of time for a regular set pulse that is to transition the PCM cell from an amorphous state to a crystalline state; and
sense, concurrently with application of the setback pulse, whether the PCM cell is in the amorphous state or the crystalline state.

17. The non-transitory computer-readable medium of claim 16 , wherein the first period of time is 1/100 th of the second period of time or greater.

18. The non-transitory computer-readable medium of claim 17 , wherein the first period of time is 1/20 th of the second period of time or less.

19. The non-transitory computer-readable medium of claim 16 , wherein the instructions when executed by a processor further cause circuitry to:
apply the setback pulse during application of the read voltage.

20. A computing device comprising:
a circuit board; and
a die coupled with the circuit board, the die including
read circuitry to apply a read voltage to a phase change memory (PCM) cell;
setback circuitry coupled to the read circuitry, to apply a setback pulse to the PCM cell in response to the application of the read voltage, wherein the setback pulse is a shorter set pulse performed for a first period of time that is shorter than a second period of time for a regular set pulse that is to transition the PCM cell from an amorphous state to a crystalline state; and
sense circuitry coupled to the setback circuitry, to sense, concurrently with application of the setback pulse, whether the PCM cell is in the amorphous state or the crystalline state.

21. The computing device of claim 20 , wherein the computing device is a mobile computing device.

Assignees

• Intel Corp

Inventors

• Kripanidhi Arjun
• Pangal Kiran
• Leem Lark-Hoon
• Srinivasan Balaji

Classifications

• G11C13/0033 Primary

  Disturbance prevention or evaluation; Refreshing of disturbed memory data · CPC title

• G11C13/0004

  comprising amorphous/crystalline phase transition cells · CPC title

• G11C13/004 Primary

  Reading or sensing circuits or methods · CPC title

• G11C2013/0066

  Verify correct writing whilst writing is in progress, e.g. by detecting onset or cessation of current flow in cell and using the detector output to terminate writing · CPC title

• G11C2013/0052

  Read process characterized by the shape, e.g. form, length, amplitude of the read pulse · CPC title