Clamp elements for phase change memory arrays

Patent metadata

Field	Value
Publication number	US-10431739-B2
Application number	US-201715858728-A
Country	US
Kind code	B2
Filing date	Dec 29, 2017
Priority date	Mar 4, 2013
Publication date	Oct 1, 2019
Grant date	Oct 1, 2019

Abstract

Clamp elements, memories, apparatuses, and methods for forming the same are disclosed herein. An example memory may include an array of memory cells and a plurality of clamp elements. A clamp element of the plurality of clamp elements may include a cell structure formed non-orthogonally relative to at least one of a bit line or a word line of the array of memory cells and may be configured to control a voltage of a respective bit line.

First claim

What is claimed is:

1. A method for forming cell structures, comprising:
forming a chalcogenic material over a plurality of contacts;
after forming the chalcogenic material, forming a mask material;
removing portions of the mask material to form a plurality of mask elements, wherein at least a mask hole is located between the plurality of mask elements and positioned non-orthogonally relative the plurality of contacts;
removing a portion of the chalcogenic material to form a plurality of chalcogenic material elements; and
forming a plurality of bit lines over the chalcogenic material elements.

2. The method of claim 1 , wherein the chalcogenic material comprises GST.

3. The method of claim 1 , further comprising:
forming a bit line cap material over the chalcogenic material.

4. The method of claim 1 , wherein said forming the plurality of bit lines comprises:
forming a bit line mask configured to provide a bit line pattern; and
removing exposed portions of the chalcogenic material between the bit line mask.

5. The method of claim 1 ; further comprising:
after forming the mask hole in the mask material, forming a spacer material.

6. The method of claim 1 , further comprising:
after forming the chalcogenic material, forming a bit line cap material over the chalcogenic material.

7. The method of claim 6 , further comprising:
forming a sealant material over the plurality of chalcogenic material elements.

8. The method of claim 7 , further comprising:
forming a filling material over the sealant material.

9. The method of claim 8 , further comprising:
removing at least a portion of the filling material and the sealant material to expose the bit line cap material.

10. The method of claim 9 , wherein the plurality of hit lines contact the exposed bit line cap material.

Assignees

• Micron Technology Inc

Inventors

• Rigano Antonino
• Pellizzer Fabio

Classifications

• G11C13/0023

  Address circuits or decoders · CPC title

• G11C13/0038

  Power supply circuits · CPC title

• G11C13/0004 Primary

  comprising amorphous/crystalline phase transition cells · CPC title

• H01L45/128

  Electricity · mapped topic

• H01L45/124

  Electricity · mapped topic