Phase change memory device with voltage control elements

Patent metadata

Field	Value
Publication number	US-9525007-B2
Application number	US-97946110-A
Country	US
Kind code	B2
Filing date	Dec 28, 2010
Priority date	Dec 28, 2010
Publication date	Dec 20, 2016
Grant date	Dec 20, 2016

Abstract

A phase change memory device with reduced programming disturbance and its operation are described. The phase change memory includes an array with word lines and bit lines and voltage controlling elements coupled to bit lines adjacent to an addressed bit line to maintain the voltage of the adjacent bit lines within an allowed range.

First claim

What is claimed is:

1. A phase change memory comprising:
a plurality of voltage control elements arranged in a first line extending in a first direction;
a plurality of phase change memory cells arranged in a second line extending in the first direction; and
a plurality of conductive lines extending in a direction perpendicular to the first direction, individual ones of the plurality of conductive lines in electrical communication with a respective one of the plurality of voltage control elements and a respective one of the plurality of phase change memory cells, wherein, between the first line and the second line, a first conductive line of the plurality of conductive lines further includes a first portion and a second portion, wherein the first portion is offset from the second portion in the first direction by a first distance such that a distance in the first direction between the first portion of the first conductive line and a portion of an adjacent conductive line of the plurality of conductive lines is different than a distance between the second portion of the first conductive line and the portion of the adjacent conductive line, wherein a width of the first conductive line in the first direction at the first portion is equal to a width of the first conductive line in the first direction at the second portion of the first conductive line, wherein the second portion of the first conductive line runs parallel with the first portion of the first conductive line and at an angle that is perpendicular to the first direction;
wherein a first portion of the adjacent conductive line is offset from a second portion of the adjacent conductive line in the first direction by a second distance, wherein the first distance is different than the second distance, wherein the second distance is an integer multiple of the first distance, and wherein the plurality of conductive lines includes at least four conductive lines, including each of the first conductive line and the adjacent conductive line, wherein the second distance is twice as long as the first distance.

2. The memory of claim 1 including bit lines and word lines perpendicular to the bit lines, the word lines crossing the bit lines at cross points, each of said cross points including either a memory cell or a voltage control element.

3. The memory of claim 1 , wherein the at least four conductive lines includes a third conductive line, wherein a first portion of the third conductive line is offset from a second portion of the third conductive line in the first direction by a third distance, wherein the third distance is three times as long as the first distance.

4. A phase change memory comprising:
a plurality of voltage control elements arranged in a first line extending in a first direction;
a plurality of phase change memory cells arranged in a second line extending in the first direction; and
a plurality of conductive lines extending in a direction perpendicular to the first direction, each of the plurality of conductive lines coupled to a respective one of the plurality of phase change memory cells, wherein a first conductive line of the plurality of conductive lines is directly coupled to a respective one of the plurality of voltage control elements in the first line, and wherein a second conductive line of the plurality of conductive lines is not directly coupled to any of the plurality of voltage control elements along the first line, wherein a respective first portion of the first conductive line is offset from a respective second portion of the first conductive line in the first direction by a first distance and a respective first portion of the second conductive line is offset from a respective second portion of the second conductive line in the first direction by a second distance, wherein the first distance is different than the second distance, wherein the respective second portion of the first conductive line runs parallel with the respective first portion of the first conductive line and at an angle that is perpendicular to the first direction,
wherein the second distance is an integer multiple of the first distance, and wherein the second distance is twice as long as the first distance.

5. The memory of claim 4 including bit lines and word lines perpendicular to the bit lines, the word lines crossing the bit lines at cross points, each of said cross points including either a memory cell or a voltage control element.

6. The memory of claim 4 , wherein the plurality of conductive lines includes a third conductive line, wherein a first portion of the third conductive line is offset from a second portion of the third conductive line in the first direction by a third distance, wherein the third distance is three times as long as the first distance.

7. The memory of claim 4 wherein the plurality of conductive lines have a sublithographic pitch.

8. The memory of claim 1 , wherein the first conductive line is directly coupled to a respective one of the plurality of voltage control elements in the first line, and wherein the adjacent conductive line is not directly coupled to any of the plurality of voltage control elements along the first line.

9. The memory of claim 4 , wherein a width of the first conductive line in the first direction at the first portion is equal to a width of the first conductive line in the first direction at the second portion.

Assignees

• Pellizzer Fabio
• Rigano Antonino
• Micron Technology Inc

Inventors

• Pellizzer Fabio
• Rigano Antonino

Classifications

• H10D89/10 Primary

  Integrated device layouts · CPC title

• G11C13/0004

  comprising amorphous/crystalline phase transition cells · CPC title

• H01L27/2463 Primary

  Electricity · mapped topic

• H01L27/0207

  Electricity · mapped topic

• H10N70/011

  Manufacture or treatment of multistable switching devices · CPC title