Clamp elements for phase change memory arrays

Patent metadata

Field	Value
Publication number	US-10141508-B2
Application number	US-201615347271-A
Country	US
Kind code	B2
Filing date	Nov 9, 2016
Priority date	Mar 4, 2013
Publication date	Nov 27, 2018
Grant date	Nov 27, 2018

Abstract

Clamp elements, memories, apparatuses, and methods for forming the same are disclosed herein. An example memory may include an array of memory cells and a plurality of clamp elements. A clamp element of the plurality of clamp elements may include a cell structure formed non-orthogonally relative to at least one of a bit line or a word line of the array of memory cells and may be configured to control a voltage of a respective bit line.

First claim

What is claimed is:

1. A method for forming cell structures, comprising:
forming a mask material having a mask hole, the mask hole formed non-orthogonally relative to a row of contacts;
forming a conductive material and a spacer material over the mask material and in a portion of the mask hole;
removing portions of the conductive material and the spacer material to expose contacts from the row of contacts underlying the mask hole and to form a plurality of conductive elements and a plurality of spacer elements; and
forming a plurality of bit lines over the plurality of conductive elements and spacer elements.

2. The method of claim 1 , further comprising:
after removing portions of the conductive material and the spacer material, forming a chalcogenic material over the plurality of conductive elements and the plurality of spacer elements.

3. The method of claim 1 , wherein said removing portions of the conductive material and the spacer material comprises:
removing horizontal portions of the conductive material and the spacer material.

4. The method of claim 1 , wherein the conductive material comprises a chalcogenic material.

5. The method of claim 1 , wherein an angle at which the mask hole is formed is based, at least in part, on a distance between centers of contacts in a word line direction, centers of contacts in a bit line direction, or a combination thereof.

6. The method of claim 1 , wherein the mask hole is formed at a 45 degree angle relative to the row of contacts.

7. The method of claim 1 , wherein removing portions of the conductive material and the spacer material comprises removing horizontal portions of the conductive material and the spacer material in the mask hole to leave the conductive material and the spacer material along a wall of the mask hole.

8. A method comprising:
forming a row of contacts;
forming a mask material on the row of contacts, the mask material having a plurality of holes formed non-orthogonally relative to the row of contacts;
forming a plurality of wall self-heating type cell structures in the holes over the row of contacts, wherein forming the plurality of wall self-heating type cell structures comprises:
forming a chalcogenic material layer over contacts from the row of contacts and the mask material,
forming spacer material layer over the chalcogenic material layer, the chalcogenic material layer and the spacer material layer are formed over the mask material and fill a portion of at least one of the plurality of holes, and
removing first portions of the chalcogenic material layer and the spacer material layer to leave second portions of the chalcogenic material layer and the spacer material layer along walls of the plurality of holes formed in the mask material, and to expose the contacts from the row of contacts underlying the at least one of the plurality of holes; and

forming a bit line over the plurality of wall self-heating type cell structures.

9. The method of claim 8 , wherein the plurality of wall-self-heating type cell structures are formed non-orthogonally with the row of contacts.

Assignees

• Micron Technology Inc

Inventors

• Rigano Antonino
• Pellizzer Fabio

Classifications

• G11C13/0038

  Power supply circuits · CPC title

• G11C13/0023

  Address circuits or decoders · CPC title

• G11C13/0004 Primary

  comprising amorphous/crystalline phase transition cells · CPC title

• H01L45/065

  Electricity · mapped topic

• H01L45/16

  Electricity · mapped topic