Clamp elements for phase change memory arrays

Patent metadata

Field	Value
Publication number	US-9520554-B2
Application number	US-201313783884-A
Country	US
Kind code	B2
Filing date	Mar 4, 2013
Priority date	Mar 4, 2013
Publication date	Dec 13, 2016
Grant date	Dec 13, 2016

Abstract

Clamp elements, memories, apparatuses, and methods for forming the same are disclosed herein. An example memory may include an array of memory cells and a plurality of clamp elements. A clamp element of the plurality of clamp elements may include a cell structure formed non-orthogonally relative to at least one of a bit line or a word line of the array of memory cells and may be configured to control a voltage of a respective bit line.

First claim

What is claimed is:

1. A memory comprising:
an array of memory cells;
first and second voltage control word lines arranged outside of the array of memory cells, wherein the first and second voltage control word lines are adjacent to one another; and
a plurality of clamp elements, each clamp element of the plurality of clamp elements including a wall self-heating type cell structure having a rectangular shape with at least one dimension oriented non-orthogonally relative to at least one of a respective bit line and a respective one of the first and second voltage control word lines and configured to control a voltage of a respective bit line, wherein the wall self-heating type cell structure includes a cap, a chalcogenic material, and a switch, and wherein the chalcogenic material is both self-heating and a phase change material, and
wherein alternating ones of the plurality of clamp elements are arranged on alternating ones of the first and second voltage control word lines.

2. The memory of claim 1 , wherein the clamp element of the plurality of clamp elements includes a voltage control diode configured to control the voltage of the respective bit line.

3. The memory of claim 1 , wherein the plurality of clamp elements includes a first set of clamp elements for odd bit lines and a second set of clamp elements for even bit lines.

4. The memory of claim 1 , wherein the wall self-heating type cell structure is oriented at an angle based, at least in part, on a distance between centers of contacts in a word line direction, centers of contacts in a bit line direction, or a combination thereof.

5. The memory of claim 4 , wherein the distance between centers of contacts in the word line direction is smaller than the distance between centers of contacts in the bit line direction.

6. The memory of claim 1 , wherein the chalcogenic material is a sole source of heat in the wall self-heating type cell structure.

7. A clamp element, comprising:
a first subtractive self-heating cell structure having a rectangular shape with at least one dimension oriented non-orthogonally relative to a first voltage control word line and a first bitline and coupled to the first bit line; and
a second subtractive self-heating cell structure having a rectangular shape with at least one dimension oriented non-orthogonally relative to a second voltage control word line and a second bitline and coupled to the second bit line, wherein the first and second subtractive self-heating cell structures include a cap, a switch, and a chalcogenic material between the cap and the switch, wherein the chalcogenic material is both self-heating and a phase change material, wherein the first and second voltage control word lines are adjacent to one another and located outside of a memory cell array and wherein the first and second bit lines are adjacent to one another and cross the first and second voltage control word lines,
wherein the first and second subtractive self-heating cell structures are clamp elements configured to control a voltage of their respective bit lines during a programming operation of a memory cell.

8. The clamp element of claim 7 , wherein the chalcogenic material is a sole source of heat in the subtractive self-heating cell structure.

9. The clamp element of claim 7 , further comprising:
a voltage control diode coupled to the first voltage control word line and the first bit tine and configured to control a voltage of the bit line during a ramp down of a programming voltage.

10. The clamp element of claim 7 , wherein the subtractive self-heating cell structure further comprises at least one of a bipolar transistor, a MOS transistor, or a combination thereof.

11. The clamp element of claim 7 , wherein the chalcogenic material has a crystalline state.

12. An apparatus, comprising:
a first voltage control word line arranged outside of a cell array;
a second voltage control word line arranged outside of the cell array and adjacent to the first voltage control word line, wherein the first and second voltage control word lines are configured to provide voltages to respective clamp elements, and wherein the first and second voltage control word lines are associated with respective subsets of clamp elements;
a plurality of clamp elements, each clamp element of the plurality of clamp elements comprising a subtractive self-heating cell structure having a rectangular shape with at least one dimension oriented at a first angle, the first angle non-orthogonal relative to a respective one of the first and second voltage control word lines, wherein each of the plurality of clamp elements are configured to control a voltage applied to an unaddressed bit line based on a voltage on their respective first and second voltage control word lines, wherein the subtractive self-heating cell structure includes a cap, a conductive element a phase change material, and a switch, wherein the conductive element and the phase change material are between the cap and the switch, and wherein the conductive element and the phase change material are chalcogenic material; and
a plurality of cells, a cell of the plurality of cells comprising a wall type cell structure oriented at a second angle, the second angle different than the first angle.

13. The apparatus of claim 12 , wherein the clamp element is a first clamp element, wherein the first clamp element is configured to clamp a first bit line and a second clamp element is configured to clamp a second bit line adjacent to the first bit line.

14. The apparatus of claim 13 , wherein the first clamp element is coupled to the first voltage control word line and the second clamp element is coupled to the second voltage control word line different than the first voltage control word line.

15. The apparatus of claim 12 , wherein the plurality of clamp elements are spaced with a first pitch and the plurality of cells are spaced with a second pitch, the first pitch greater than the second pitch.

16. The apparatus of claim 12 , wherein the first angle is based, at least in part, on a distance between centers of contacts in a word line direction, centers of contacts in a bit line direction, or a combination thereof.

17. The apparatus of claim 16 , wherein the distance between centers of contacts in the word line direction is smaller than the distance between centers of contacts in the bit line direction.

Assignees

• Micron Technology Inc

Inventors

• Rigano Antonino
• Pellizzer Fabio

Classifications

• G11C13/0023

  Address circuits or decoders · CPC title

• G11C13/0038

  Power supply circuits · CPC title

• G11C13/0004 Primary

  comprising amorphous/crystalline phase transition cells · CPC title

• H01L27/2463

  Electricity · mapped topic

• H01L45/06

  Electricity · mapped topic