Multi-level signaling in memory with wide system interface

Patent metadata

Field	Value
Publication number	US-10425260-B2
Application number	US-201715854600-A
Country	US
Kind code	B2
Filing date	Dec 26, 2017
Priority date	Aug 7, 2017
Publication date	Sep 24, 2019
Grant date	Sep 24, 2019

Abstract

Techniques are provided herein to increase a rate of data transfer across a large number of channels in a memory device using multi-level signaling. Such multi-level signaling may be configured to increase a data transfer rate without increasing the frequency of data transfer and/or a transmit power of the communicated data. An example of multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the multi-level signal may be configured to represent a plurality of bits of data.

First claim

What is claimed is:

1. An electronic memory apparatus, comprising:
an array of memory cells;
a controller configured to control access to the array of memory cells;
an interposer to operatively couple the array of memory cells with the controller, the interposer including a plurality of channels between the array of memory cells and the controller;
a substrate coupled with the interposer and formed of a first material, wherein the interposer is formed of a second material different than the first material; and
a receiver configured to decode a multi-level signal modulated using a first modulation scheme having at least three levels communicated across at least one channel of the interposer.

2. The apparatus of claim 1 , further comprising:
a driver configured to generate the multi-level signal to be transmitted across the at least one channel of the interposer based at least in part on a plurality of information bits.

3. The apparatus of claim 1 , wherein the receiver further comprises:
a plurality of comparators, each comparator configured to compare the multi-level signal to a voltage threshold.

4. The apparatus of claim 3 , wherein the receiver further comprises:
a decoder configured to determine a plurality of bits represented by the multi-level signal based at least in part on information received from a set of the plurality of comparators.

5. The apparatus of claim 1 , wherein:
a plurality of information bits are represented by an amplitude of the multi-level signal.

6. The apparatus of claim 1 , wherein:
the multi-level signal is encoded with information using a pulse-amplitude modulation (PAM) scheme.

7. The apparatus of claim 1 , wherein:
the controller transmits the multi-level signal across a subset of the plurality of channels of the interposer to the array of memory cells.

8. An electronic memory apparatus, comprising:
an array of memory cells;
a controller configured to control access to the array of memory cells;
an interposer to operatively couple the array of memory cells with the controller, the interposer including a plurality of channels between the array of memory cells and the controller, wherein the controller transmits a multi-level signal using a unidirectional channel of the interposer; and
a receiver configured to decode the multi-level signal modulated using a first modulation scheme having at least three levels communicated across at least one channel of the interposer.

9. The apparatus of claim 1 , wherein:
the array of memory cells transmits the multi-level signal across a subset of the plurality of channels of the interposer to the controller.

10. The apparatus of claim 1 , wherein:
the second material comprises silicon.

11. The apparatus of claim 1 , further comprising:
a second array of memory cells stacked on top of the array of memory cells, wherein the second array of memory cells is operatively coupled with the controller by the interposer.

12. The apparatus of claim 1 , further comprising:
an input/output device coupled with the array of memory cells and the interposer, wherein the input/output device is configured to buffer information communicated with the array of memory cells.

13. The apparatus of claim 1 , further comprising:
a driver configured to encode data using gray coding or data bus inversion or both.

14. A method, comprising:
identifying, by a controller of a memory device, information to be written to an array of memory cells;
generating, by the controller, a multi-level signal modulated using a first modulation scheme having at least three levels that represent a plurality of bits of the identified information; and
transmitting simultaneously, by the controller, the multi-level signal and a binary-level signal to the array of memory cells across an interposer that includes a plurality of channels.

15. The method of claim 14 , further comprising:
determining, by the array of memory cells, whether an amplitude of the multi-level signal satisfies one or more thresholds.

16. The method of claim 15 , further comprising:
identifying, by the array of memory cells, the plurality of bits represented by the multi-level signal based at least in part on a number of thresholds of the one or more thresholds that are satisfied by the multi-level signal.

17. The method of claim 16 , further comprising:
writing, by the array of memory cells, the plurality of bits represented by the multi-level signal to one or more memory cells of the array of memory cells.

18. An electronic memory apparatus, comprising:
an array of memory cells;
an interposer operatively coupled with the array of memory cells, the interposer that includes a plurality of channels;
a substrate coupled with the interposer and formed of a first material, wherein the interposer is formed of a second material different than the first material; and
a controller operatively coupled with the interposer, the controller configured to:
identify information to be written to the array of memory cells;
generate a multi-level signal modulated using a first modulation scheme having at least three levels that represent a plurality of bits of the identified information; and
transmit the multi-level signal to the array of memory cells across the interposer.

Assignees

• Micron Technology Inc

Inventors

• Hollis Timothy M
• Balb Markus
• Ebert Ralf

Classifications

• G11C7/1057 Primary

  Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load · CPC title

• G11C7/1096

  Write circuits, e.g. I/O line write drivers · CPC title

• G11C7/1084

  Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load · CPC title

• H04L25/4917 Primary

  using multilevel codes · CPC title

• H04L25/4921

  using quadrature encoding, e.g. carrierless amplitude-phase coding · CPC title