Apparatuses and methods for asymmetric bi-directional signaling incorporating multi-level encoding

Patent metadata

Field	Value
Publication number	US-9577854-B1
Application number	US-201514831517-A
Country	US
Kind code	B1
Filing date	Aug 20, 2015
Priority date	Aug 20, 2015
Publication date	Feb 21, 2017
Grant date	Feb 21, 2017

Abstract

Apparatuses and methods for asymmetric bi-directional signaling incorporating multi-level encoding are disclosed. An example apparatus may include first and second channels, a receiver coupled to the first and second channels, and first and second transmitters coupled to the first and second channels, respectively. The receiver may be configured to receive differential data signals to receive write data at a rate, and each of the first and second transmitters may be configured to encode a plurality of bits into a respective data signal and provide the respective data signals at the data rate.

First claim

What is claimed is:

1. An apparatus, comprising:
first and second channels;
a receiver coupled to the first and second channels and configured to receive differential data signals to receive first data at a first data rate; and
first and second transmitters coupled to the first and second channels, respectively, each transmitter configured to encode a plurality of bits into a respective data signal and provide the respective data signals at a second data rate, wherein a summation of the respective data signal at the second data rate equals the first data rate,
wherein each transmitter encodes the plurality of bits based on a pulse amplitude modulation encoding method.

2. The apparatus of claim 1 , wherein each of the first and second transmitters comprises:
an encoder configured to encode the plurality of bits into the data signal; and
a driver coupled to the encoder and configured to receive the data signal and provide the data signal.

3. The apparatus of claim 1 , wherein the differential data signals are received from a controller and wherein the data signals are provided to the controller.

4. The apparatus of claim 1 , wherein the transmitter encodes the plurality of bits into one of a plurality of voltage levels.

5. The apparatus of claim 4 , wherein the plurality of bits is two bits and wherein the plurality of voltage levels is four voltage levels.

6. The apparatus of claim 1 , wherein the pulse amplitude modulation encoding method is a four-level pulse amplitude modulation encoding method.

7. The apparatus of claim 1 , wherein the first data rate is twice the second data rate.

8. An apparatus, comprising:
a receiver configured to receive un-encoded differential data signals;
first and second encoders configured to encode a respective plurality of bits into a respective encoded data signal, wherein the data signal is provided at one of a plurality of voltage levels, and wherein the one of the plurality of voltage levels is indicative of a bit combination of the plurality of bits; and
first and second drivers coupled to the first and second encoders, respectively, and configured to provide the respective encoded data signals.

9. The apparatus of claim 8 , wherein the first and second encoders are each configured to encode the respective plurality of bits into a respective one of a plurality of voltage levels, wherein a logic level of each of the respective plurality of bits determines the respective one of the plurality of voltage levels.

10. The apparatus of claim 9 , wherein each of the respective plurality of bits are two bits and wherein the plurality of voltage levels is four voltage levels.

11. The apparatus of claim 8 , wherein the receiver comprises a plurality of fractional-rate receivers, and wherein each of the plurality of fractional-rate receivers are configured to receive the un-encoded differential data signals at a first data rate based on a first clock rate, and the respective data signals are provided at half the first data rate based on a second clock rate.

12. The apparatus of claim 11 , wherein the first and second clock rates are different.

13. An apparatus, comprising:
a receiver configured to receive un-encoded differential data signals, the receiver includes a plurality of fractional-rate receivers, wherein each of the plurality of fractional-rate receivers are configured to receive the un-encoded differential data signals at a first data rate based on a first clock rate, and the respective data signals are provided at half the first data rate based on a second clock rate, and wherein the second clock rate is less the first clock rate;
first and second encoders configured to encode a respective plurality of bits into a respective encoded data signal; and
first and second drivers coupled to the first and second encoders, respectively, and configured to provide the respective encoded data signals.

14. An apparatus, comprising:
a receiver configured to receive un-encoded differential data signals;
first and second encoders configured to encode a respective plurality of bits into a respective encoded data signal, wherein the encoded data signal is encoded based on four-level pulse amplitude modulation; and
first and second drivers coupled to the first and second encoders, respectively, and configured to provide the respective encoded data signals.

15. A method, comprising:
receiving a differential data signal at a first data rate;
encoding a plurality of bits into an encoded data signal, wherein the encoded data signal corresponds to one of a plurality of voltage levels; and
transmitting an encoded data signal at a second data rate, wherein the second data rate is based on a number of bits in the plurality of bits encoded into the data signal,
wherein the differential data is received at the first data rate based on a first clock rate, and the encoded data signal is transmitted at the second data rate based on a second clock rate, and wherein the second clock rate is less than the first clock rate.

16. The method of claim 15 , wherein the plurality of bits is two bits, and wherein the plurality of voltage levels is four voltage levels.

17. The method of claim 16 , wherein logic levels of the two bits are encoded into a respective one of the four voltage levels.

18. The method of claim 15 , wherein the second data rate is half the first data rate.

19. A method, comprising:
receiving differential data signals;
encoding a first plurality of bits into a first encoded data signal characterized by one of a plurality of voltage levels;
encoding a second plurality of bits into a second encoded data signal characterized by one of the plurality of voltage levels; and
transmitting the first and second encoded data signals,
wherein transmitting the first and second encoded data signals comprises transmitting each of the first and second encoded data signals responsive to a clock rate, wherein the clock rate is based at least in part on a number of bits encoded into each of the first and second encoded data signals.

20. The method of claim 19 , wherein encoding a first plurality of bits into an encoded data signal characterized by one of a plurality of voltage levels comprises encoding two bits into an encoded data signal characterized by one of four voltage levels.

21. The method of claim 19 , wherein the one of the plurality of voltage levels is indicative of a logic level of each bit of the first and second plurality of bits, respectively.

22. A method, comprising:
receiving differential data signals;
encoding a first plurality of bits into a first encoded data signal characterized by one of a plurality of voltage levels;
encoding a second plurality of bits into a second encoded data signal characterized by one of the plurality of voltage levels; and
transmitting the first and second encoded data signals, wherein the differential signals are received at a first data rate based on a first clock rate, and the first and second encoded data signals are transmitted at a second data rate based on a second clock rate, and wherein the first clock rate is greater than the second clock rate, and wherein the second data rate is half the first data rate.

23. An apparatus, comprising:
first and second channels;
a receiver coupled to the first and second channels and configured to receive differential data signals to receive first data at a first data rate; and
first and second transmitters coupled to the first and se

Assignees

• Micron Technology Inc

Inventors

• Hollis Timothy

Classifications

• H04L27/02

  Amplitude-modulated carrier systems, e.g. using on-off keying; Single sideband or vestigial sideband modulation (H04L27/32 takes precedence) · CPC title

• G06F13/4068

  Electrical coupling · CPC title

• H04L25/4917 Primary

  using multilevel codes · CPC title

• G06F13/1689 Primary

  Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234) · CPC title

• G06F1/324

  by lowering clock frequency · CPC title