Voltage control for crosspoint memory structures

Patent metadata

Field	Value
Publication number	US-2016189775-A1
Application number	US-201314908667-A
Country	US
Kind code	A1
Filing date	Jul 31, 2013
Priority date	Jul 31, 2013
Publication date	Jun 30, 2016
Grant date	—

Abstract

The present disclosure provides a memory cell that includes a resistive memory element disposed between a first conductor and a second conductor, the first conductor and the second conductor configured to activate the resistive memory element. The memory cell also includes a diode disposed in parallel with the memory element between the first conductor and the second conductor.

First claim

What is claimed is:

1 . A memory cell, comprising:
a resistive memory element disposed between a first conductor and a second conductor, the first conductor and the second conductor configured to activate the resistive memory element; and a diode disposed in parallel with the memory element between the first conductor or the second conductor.

2 . The memory cell of claim 1 , wherein the resistive memory element comprises at least one of a memristor, a Phase Change Material resistor, a conductive bridge resistor, and a transition metal oxide based resistor.

3 . The memory cell of claim 1 , wherein a first conduction threshold voltage of the diode is approximately equal to a designed set voltage of the memory element and a second conduction threshold voltage of the diode is approximately equal to a designed reset voltage of the memory element.

4 . The memory cell of claim 3 , wherein the first conduction threshold voltage of the diode is the forward conduction mode threshold voltage and a second conduction threshold voltage of the diode is the reverse conduction mode threshold voltage.

5 . The memory cell of claim 1 , wherein the diode is a Zener diode or an avalanche diode.

6 . A data storage device, comprising
a memory cell array comprising a plurality memory cells; word lines electrically coupled to the plurality of memory cells; and bit lines electrically coupled to the plurality of memory cells, wherein each memory cell in the plurality of memory cells lies at a crosspoint of one of the word lines and one of the bit lines; wherein each of the plurality of memory cells comprises:
a resistive memory element disposed between one of the word lines and one of the bit lines; and
a diode disposed in parallel with the memory element between the the word line and the bit line.

7 . The data storage device of claim 6 , wherein the resistive memory element comprises at least one of a Resistive Random Access Memory (RRAM) element, a Spin-Transfer Torque Random Access Memory (STT-RAM) element, a conductive bridge resistor, and a transition metal oxide based resistor.

8 . The data storage device of claim 6 , wherein a first conduction threshold voltage of the diode is approximately equal to a designed set voltage of the memory element and a second conduction threshold voltage of the diode is approximately equal to a designed reset voltage of the memory element.

9 . The data storage device of claim 8 , wherein the first conduction threshold voltage of the diode is the forward conduction mode threshold voltage and a second conduction threshold voltage of the diode is the reverse conduction mode threshold voltage.

10 . The data storage device of claim 6 , wherein the memory cell array is a multi-layer array comprising alternating layers of memory cells, bit lines, and word lines.

11 . The data storage device of claim 6 , wherein a selected memory cell is configured to be read by applying a voltage across the word line and the bit line corresponding to the selected memory cell, a magnitude of the voltage being less than a magnitude of a threshold voltage of the diode.

12 . A method of forming a memory cell, comprising:
disposing a resistive memory element between two electrodes; disposing a diode in parallel with the resistive memory element between the two electrodes.

13 . The method of claim 12 , wherein disposing the resistive memory element comprises forming a memristor.

14 . The method of claim 12 , wherein disposing the diode comprises forming a zener diode or an avalanche diode.

15 . The method of claim 12 , wherein disposing the diode comprises forming a diode with a first conduction threshold voltage approximately equal to a designed set voltage of the memory element and a second conduction threshold voltage approximately equal to a designed reset voltage of the memory element.

Assignees

• Hewlett Packard Entpr Dev Lp

Inventors

• Buchanan Brent Edgar

Classifications

• H10D8/20

  Breakdown diodes, e.g. avalanche diodes · CPC title

• G11C13/003 Primary

  Cell access · CPC title

• H10D8/25

  Zener diodes · CPC title

• H10D8/024

  of Avalanche diodes · CPC title

• H10D8/022

  of Zener diodes · CPC title