Power semiconductor devices, semiconductor devices and a method for adjusting a number of charge carriers

Patent metadata

Field	Value
Publication number	US-10424636-B2
Application number	US-201615386077-A
Country	US
Kind code	B2
Filing date	Dec 21, 2016
Priority date	Dec 21, 2015
Publication date	Sep 24, 2019
Grant date	Sep 24, 2019

Abstract

A power semiconductor device includes a semiconductor substrate including at least one electrical structure. The at least one electrical structure has a blocking voltage of more than 20V. Further, the power semiconductor device includes an electrically insulating layer structure formed over at least a portion of a lateral surface of the semiconductor substrate. The electrically insulating layer structure embeds one or more local regions for storing charge carriers. Further, the one or more local regions includes in at least one direction a dimension of less than 200 nm.

First claim

What is claimed is:

1. A power semiconductor device comprising:
a semiconductor substrate comprising at least one electrical structure, wherein the at least one electrical structure has a blocking voltage of more than 20V; and
an electrically insulating layer structure formed over at least a portion of a lateral surface of the semiconductor substrate, wherein the electrically insulating layer structure extends along an edge termination region of the semiconductor substrate,
wherein the electrically insulating layer structure embeds a plurality of local regions configured to store charge carriers, wherein defined charge carriers are impressed in the edge termination region so that a charge carrier distribution varies laterally, wherein the plurality of local regions comprise, in at least one direction, a dimension of less than 200 nm, wherein the plurality of local regions for storing the charge carriers are at least one of the group of nano-particles and nano-crystals.

2. The power semiconductor device according to claim 1 , wherein a current of the charge carriers from the plurality of local regions to the semiconductor substrate is less than 1*10 −17 A/cm 2 during normal operation of the power semiconductor device.

3. The power semiconductor device according to claim 1 , wherein the plurality of local regions are electrically floating regions within the electrically insulating layer structure.

4. The power semiconductor device according to claim 1 , wherein the plurality of local regions are distributed over at least a portion of the electrically insulating layer structure comprising a thickness of more than 50 nm.

5. The power semiconductor device according to claim 1 , wherein a maximal dimension of each local region of the plurality of local regions is less than 200 nm.

6. The power semiconductor device according to claim 1 , wherein a density of local regions of the plurality of local regions within at least a portion of the electrically insulating layer structure is larger than 1*10 9 local regions per cm 2 .

7. The power semiconductor device according to claim 1 , wherein a local density of local regions per volume vary by less than 10% of an average density of local regions per volume within the electrically insulating layer structure or sub-portions of the electrically insulating layer structure.

8. The power semiconductor device according to claim 1 , wherein an average distance of each local region of the plurality of local regions to a closest neighboring local region of the plurality of local regions is less than 10% of an average distance of the local regions of the plurality of local regions to the lateral surface of the semiconductor substrate.

9. The power semiconductor device according to claim 1 , wherein the plurality of local regions are distributed laterally over more than 10 μm.

10. The power semiconductor device according to claim 1 , wherein the electrically insulating layer structure is one of the group of a silicon oxide layer, a silicon nitride layer, an aluminum oxide layer and a polymer layer.

11. The power semiconductor device according to claim 1 , wherein the charge carriers stored by the plurality of local regions embedded within the electrically insulating layer structure cause an electric field of more than 1*10 5 volts per meter at an interface between the electrically insulating layer structure and a passivation layer or between the electrically insulating layer structure and a molding material or potting gel of a package of the power semiconductor device in a non-operating state of the power semiconductor device.

12. The power semiconductor device according to claim 1 , wherein a number of the charge carriers stored by the plurality of local regions embedded within the electrically insulating layer structure comprises a lateral variation of an average charge per volume.

13. The power semiconductor device according to claim 1 , wherein:
the electrically insulating layer structure embeds the plurality of local regions configured to store the charge carriers,
the plurality of local regions are distributed over at least a portion of the electrically insulating layer structure comprising a thickness of more than 50 nm, and
the plurality of local regions are at least one of the group of nano-particles and nano-crystals.

14. The power semiconductor device according to claim 1 , wherein:
the electrically insulating layer structure embeds the plurality of local regions configured to store the charge carriers,
a current of the charge carriers from the plurality of local regions to the semiconductor substrate is less than 1*10 −17 A/cm 2 during normal operation of the power semiconductor device,
at least a portion of the electrically insulating layer structure embeds an average amount of the charge carriers per volume of more than 1*10 −8 Coulomb per cm 2 stored by the plurality of local regions, and the plurality of local regions are at least one of the group of nano-particles and nano-crystals.

15. The power semiconductor device according to claim 1 , wherein:
the electrically insulating layer structure embeds the plurality of local regions configured to store the charge carriers,
a charge stored by the plurality of local regions embedded within the electrically insulating layer structure causes an electric field of more than 1*10 5 volts per meter at an interface between the electrically insulating layer structure and a passivation layer or between the electrically insulating layer structure and a molding material of a package of the semiconductor device in a non-operating state of the semiconductor device, and
the plurality of local regions are at least one of the group of nano-particles and nano-crystals.

16. A power semiconductor device comprising:
a semiconductor substrate comprising at least one electrical structure, wherein the at least one electrical structure has a blocking voltage of more than 20V;
at least one trench extending from a surface of the semiconductor substrate into the semiconductor substrate; and
an electrically insulating layer structure formed within the at least one trench, wherein the electrically insulating layer structure embeds a plurality of local regions configured to store charge carriers, wherein defined charge carriers are impressed in an edge termination region of the semiconductor substrate so that a charge carrier distribution varies laterally, wherein a density of local regions of the plurality of local regions within at least a portion of the electrically insulating layer structure is larger than 1*10 13 local regions per cm 3 , wherein the plurality of local regions for storing the charge carriers are at least one of the group of nano-particles and nano-crystals.

17. A power semiconductor device comprising:
a semiconductor substrate comprising at least one electrical structure, wherein the at least one electrical structure has a blocking voltage of more than 20V; and
an electrically insulating layer structure formed over at least a portion of a lateral surface of the semiconductor substrate, wherein the electrically insulating layer structure extends along an edge termination region of the semiconductor substrate,
wherein the electrically insulating layer structure includes a plurality of first portions and a plurality of second portions that laterally alternate on an individual basis with the plurality of first portions,
wherein each of the plurality of first portions embeds a plurality of local regions configured to store charge carriers, wherein each of the plurality of local regio

Assignees

• Infineon Technologies Ag

Inventors

• Haertl Andreas
• Brandt Martin
• Stegner Andre Rainer
• Stutzmann Martin

Classifications

• H10W10/50

  Isolation regions based on field-effect · CPC title

• H10W10/051

  of isolation region based on field-effect · CPC title

• H01L29/0649

  Electricity · mapped topic

• H01L29/0684

  Electricity · mapped topic

• H01L29/407

  Electricity · mapped topic