Sub 59 MV/decade SI CMOS compatible tunnel FET as footer transistor for power gating

Patent metadata

Field	Value
Publication number	US-10424581-B2
Application number	US-201615276768-A
Country	US
Kind code	B2
Filing date	Sep 26, 2016
Priority date	Apr 18, 2016
Publication date	Sep 24, 2019
Grant date	Sep 24, 2019

Abstract

An integrated circuit (IC) including a circuit block including a plurality of complementary metal oxide semiconductor field-effect transistors (CMOSFETs), and a tunnel field-effect transistor (TFET) between the circuit block and ground for power gating the circuit block.

First claim

What is claimed is:

1. An integrated circuit (IC) comprising:
a circuit block coupled to a supply voltage and comprising a plurality of complementary metal oxide semiconductor field-effect transistors (CMOSFETs); and
a tunnel field-effect transistor (TFET) between the circuit block and ground for power gating the circuit block by blocking an amount of current flowing from the circuit block to ground during a standby mode,
wherein the circuit block is between the TFET and the supply voltage.

2. The IC of claim 1 , wherein a subthreshold slope of the TFET is less than or equal to about 59 mV/decade at room temperature.

3. The IC of claim 1 , wherein the TFET comprises a group IV material.

4. The IC of claim 1 , wherein the TFET comprises a drain region and a source region, and
wherein dopants of CMOSFETs of the circuit block and dopants of the drain region of the TFET or of the source region of the TFET comprise a group V or group III material.

5. The IC of claim 1 , wherein a gate region of the TFET overlaps a source region of the TFET to a greater degree than the gate region of the TFET overlaps a drain region of the TFET.

6. The IC of claim 1 , wherein the TFET is an n-type TFET.

7. The IC of claim 1 , wherein the TFET is connected through a Via1 to a virtual ground terminal metal at a Metal1 level of the IC.

8. The IC of claim 1 , wherein the TFET has a gate length that is greater than or equal to about twice a gate length of an average CMOSFET of the circuit block.

9. The IC of claim 1 , wherein the TFET has a width that is greater than or equal to about five times a width of an average CMOSFET of the circuit block.

10. A method of integrated circuit (IC) fabrication the method comprising:
preparing a silicon substrate;
masking off TFET regions;
preparing CMOSFETs corresponding to a circuit block of the IC;
unmasking the TFET regions; and
preparing a plurality of TFETs at the TFET regions by:
preparing gates of the TFETs by reusing gate length masks used for preparing input/output (I/O) or static random-access memory (SRAM) devices;
forming nitride spacers on both sides of the gates; and
doping the TFET regions,

wherein the TFETs are for power gating the circuit block by blocking an amount of current flowing from the circuit block to ground during a standby mode, the circuit block being between the TFETs and ground.

11. The method of claim 10 , wherein doping the TFET regions comprises:
lightly doping the TFET region with p-type dopants;
masking gate regions and source regions of the TFET regions;
doping drain regions of the TFET regions;
unmasking the source regions and masking the drain regions;
recessing a silicon layer; and
doping the source regions with p-type dopants.

12. The method of claim 10 , wherein preparing the gates comprises forming gate lengths of the TFETs to be longer than gate lengths of the CMOSFETs of the circuit block.

13. The method of claim 10 , wherein preparing the TFETs at the TFET regions further comprises forming replacement metal gates as gates of the TFETs.

14. The method of claim 13 , wherein forming replacement metal gates as gates of the TFETs comprises depositing a high dielectric constant (HiK) oxide and an appropriate n-type workfunction metal.

15. The method of claim 10 , further comprising connecting the TFETs to a virtual ground terminal of the circuit block at a Metal1 level of the IC.

16. The method of claim 10 , wherein preparing the TFETs at the TFET regions comprises forming the TFETs to be wider than the CMOSFETs of the circuit block.

17. A logic microprocessor comprising:
a circuit block coupled to a supply voltage and comprising complementary metal oxide semiconductor field-effect transistors (CMOSFETs); and
one or more tunnel field-effect transistors (TFETs) for power gating the circuit block by blocking an amount of current flowing from the circuit block to ground during a standby mode,
wherein the circuit block is between the one or more TFETs and the supply voltage, and
wherein the one or more TFETs are between ground and the circuit block.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Rakshit Titash
• Rodder Mark
• Sengupta Rwik

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H01L21/823814

  Electricity · mapped topic

• H01L29/7391

  Electricity · mapped topic

• H01L23/5226

  Electricity · mapped topic