Tunnel field-effect transistor (TFET) based high-density and low-power sequential

Patent metadata

Field	Value
Publication number	US-9985611-B2
Application number	US-201514922072-A
Country	US
Kind code	B2
Filing date	Oct 23, 2015
Priority date	Oct 23, 2015
Publication date	May 29, 2018
Grant date	May 29, 2018

Abstract

Described is an apparatus which comprises: a first p-type Tunneling Field-Effect Transistor (TFET); a first n-type TFET coupled in series with the first p-type TFET; a first node coupled to gate terminals of the first p-type and n-type TFETs; a first clock node coupled to a source terminal of the first TFET, the first clock node is to provide a first clock; and a second clock node coupled to a source terminal of the second TFET, the second clock node is to provide a second clock.

First claim

We claim:

1. An apparatus comprising:
a first p-type Tunneling Field-Effect Transistor (TFET);
a first n-type TFET directly connected in series with the first p-type TFET;
a first node coupled to gate terminals of the first p-type and n-type TFETs;
a first clock node directly connected to a source terminal of the first p-type TFET, the first clock node is to provide a first clock;
a second clock node coupled to a source terminal of the first n-type TFET, the second clock node is to provide a second clock;
a first TFET inverter having an input coupled to drain terminals of the first p-type and n-type TFETs, respectively, and an output;
a second p-type TFET having a source terminal coupled to the second clock node and a gate terminal coupled to the output of the first TFET inverter, wherein drain terminal of the second p-type TFET is coupled to the drain terminal of the first p-type TFET; and
a third p-type TFET having a source terminal coupled to the second clock node, and having a gate terminal coupled to the output of the first TFET inverter.

2. The apparatus of claim 1 comprises:
a second n-type TFET coupled in series with the second p-type TFET, the second n-type TFET having a source terminal coupled to the first clock node, and having a gate terminal coupled to the output of the first TFET inverter.

3. The apparatus of claim 2 , wherein drain terminal of the second n-type TFET is coupled to the drain terminals of the first p-type and n-type TFETs.

4. The apparatus of claim 2 comprises:
a third n-type TFET coupled in series with the third p-type TFET, the third n-type TFET having a source terminal coupled to the first clock node, and having a gate terminal coupled to the output of the first TFET inverter.

5. The apparatus of claim 4 comprises:
a second TFET inverter having an input coupled to drain terminals of the third p-type and n-type TFETs, respectively, and an output.

6. The apparatus of claim 5 comprises:
a fourth p-type TFET having a source terminal coupled to the first clock node, and having a gate terminal coupled to the output of the second TFET inverter; and
a fourth n-type TFET coupled in series with the fourth p-type TFET, the fourth n-type TFET having a source terminal coupled to the second clock node, and having a gate terminal coupled to the output of the second TFET inverter.

7. The apparatus of claim 6 , wherein drain terminals of the fourth p-type and n-type TFETs are coupled to the drain terminals of the third p-type and n-type TFETs.

8. The apparatus of claim 6 comprises:
a third TFET inverter having an input coupled to drain terminals of the third p-type and n-type TFETs, respectively, and an output.

9. The apparatus of claim 1 comprises a pair of inverters to generate the first and second clocks from a clock source.

10. The apparatus of claim 1 , wherein the second clock is an inverse of the first clock.

11. An apparatus comprising:
a first clock node to provide a first clock;
a second clock node to provide a second clock, the second clock is to be an inverse of the clock;
a first pair of Tunneling Field-Effect Transistors (TFETs) including:
a p-type TFET having a source terminal directly connected to the clock node;
a n-type TFET directly connected in series with the p-type TFET, the n-type TFET having a source terminal coupled to the second clock node; and
a node coupled to gate terminals of the p-type and n-type TFETs, the node is to receive an input signal;

a second pair of TFETs including:
a p-type TFET having a source terminal coupled to the second clock; and
a n-type TFET coupled in series with the p-type TFET of the second pair, the n-type TFET of the second pair having a source terminal coupled to the clock;

wherein gate terminals of the p-type and n-type TFETs of the second pair are coupled to the node of the pair of TFETs;
a first inverter having an input coupled to drain terminals of the n-type and p-type TFETs of the pair of TFETs; and
a third pair of TFETs including:
a p-type TFET having a source terminal coupled to the second clock node;
a n-type TFET coupled in series with the p-type TFET of the third pair, the n-type TFET having a source terminal coupled to the clock node; and
a node coupled to gate terminals of the p-type and n-type TFETs of the third pair of TFETs, and also coupled to an output of the first inverter.

12. The apparatus of claim 11 comprises:
a second inverter having an input coupled to drain terminals of the n-type and p-type TFETs of the second pair of TFETs.

13. The apparatus of claim 12 , wherein drain terminals of p-type and n-type TFETs of the third pair are coupled to the input of the first inverter.

14. The apparatus of claim 13 comprises a fourth pair of TFETs including:
a p-type TFET having a source terminal coupled to the first clock node;
a n-type TFET coupled in series with the p-type TFET of the fourth pair, the n-type TFET having a source terminal coupled to the second clock node; and
a node coupled to gate terminals of the p-type and n-type TFETs of the fourth pair of TFETs, and also coupled to an output of the second inverter, wherein drain terminals of p-type and n-type TFETs of the fourth pair are coupled to the input of the second inverter.

15. The apparatus of claim 14 , comprises a fifth pair of TFETs including:
a p-type TFET having a source terminal to receive the second clock;
a n-type TFET coupled in series with the p-type TFET of the fifth pair, the n-type TFET having a source terminal to receive the first clock; and
a node coupled to gate terminals of the p-type and n-type TFETs of the fifth pair of TFETs, and also coupled to an output of the first inverter.

16. The apparatus of claim 15 , comprises a sixth pair of TFETs including:
a p-type TFET having a source terminal coupled to the first clock node;
a n-type TFET coupled in series with the p-type TFET of the sixth pair, the n-type TFET having a source terminal coupled to the second clock node; and
a node coupled to gate terminals of the p-type and n-type TFETs of the sixth pair of TFETs, and also coupled to an output of the second inverter.

17. The apparatus of claim 16 , comprises a third inverter having an input coupled the fifth and sixth pair of TFETs.

18. A system comprising:
a memory;
a processor coupled to the memory, the processor includes a flip-flop which comprises:
a first p-type Tunneling Field-Effect Transistor (TFET);
a first n-type TFET directly connected in series with the first p-type TFET;
a first node coupled to gate terminals of the first p-type and n-type TFETs;
a first clock node directly connected to a source terminal of the first p-type TFET, the first clock node is to provide a first clock; and
a second clock node coupled to a source terminal of the first n-type TFET, the second clock node is to provide a second clock; and

a wireless interface for allowing the processor to communicate with another device.

19. The system of claim 18 , wherein the flip-flop comprises:
a first TFET inverter having an input coupled to drain terminals of the first p-type and n-type TFETs, respectively, and an output.

20. The system of claim 18 , wherein the flip-flop includes a combination of MOSFETs and TFETs.

Assignees

• Intel Corp

Inventors

• Morris Daniel H
• Avci Uygar E
• Young Ian A

Classifications

• H03K3/35625

  using complementary field-effect transistors · CPC title

• H03K3/356113 Primary

  using additional transistors in the input circuit · CPC title

• H03K3/3562

  of the primary-secondary type · CPC title

• H03K3/012 Primary

  Modifications of generator to improve response time or to decrease power consumption · CPC title

• H01L29/66977

  Electricity · mapped topic