Memory device with a multi-mode communication mechanism

Patent metadata

Field	Value
Publication number	US-10419574-B2
Application number	US-201715684831-A
Country	US
Kind code	B2
Filing date	Aug 23, 2017
Priority date	Aug 23, 2017
Publication date	Sep 17, 2019
Grant date	Sep 17, 2019

Abstract

A memory device includes a memory array including a first communication circuit element configured to communicate a first signal between components in the memory device; a second communication circuit element configured to communicate a second signal between the components in the memory device; and a configurable grouping mechanism coupled to the first communication circuit element and the second communication circuit element, the configurable grouping mechanism configured to select between: operating the first communication circuit element and the second communication circuit element independent of each other, where in the first signal and the second signal are independent signals, and operating the first communication circuit element and the second communication circuit element as a group, wherein the first signal corresponds to the second signal.

First claim

We claim:

1. A memory device, comprising:
a first communication circuit element configured to communicate a first signal between components in the memory device;
a second communication circuit element configured to communicate a second signal between the components in the memory device, wherein the second signal is communicated in parallel with the first signal between the components; and
a configurable grouping mechanism coupled to the first communication circuit element and the second communication circuit element, the configurable grouping mechanism configured to select between:
operating the first communication circuit element and the second communication circuit element independent of each other, wherein the first signal and the second signal are independent signals, and
operating the first communication circuit element and the second communication circuit element as a group, wherein the first signal corresponds to the second signal.

2. The memory device of claim 1 wherein the configurable grouping mechanism is configured to make a selection to operate the first communication circuit element and the second communication circuit element as a group, wherein the first signal and the second signal are complementary to each other.

3. The memory device of claim 2 wherein the first signal and the second signal are a differential pair.

4. The memory device of claim 1 wherein the memory device is a NAND Flash device.

5. The memory device of claim 4 wherein the configurable grouping mechanism is configured to make a selection to operate the first communication circuit element and the second communication circuit element independent of each other to implement Open NAND Flash Interface (ONFI) communication.

6. The memory device of claim 1 further comprising:
a first transmitter coupled to the first communication circuit element and the configurable grouping mechanism, the first transmitter configured to send the first signal; and
a second transmitter coupled to the second communication circuit element and the configurable grouping mechanism, the second transmitter configured to send the second signal.

7. The memory device of claim 6 wherein the configurable grouping mechanism is configured to electrically couple the first transmitter to the second communication circuit element for operating the first communication circuit element and the second communication circuit element as a group.

8. The memory device of claim 7 further comprising an inverter coupled to the first transmitter, the inverter configured to generate the first signal or the second signal as an inverted signal of the other.

9. The memory device of claim 6 wherein the configurable grouping mechanism is configured to isolate the first transmitter and the second transmitter to independently operate the first communication circuit element and the second communication circuit element, wherein the configurable grouping mechanism isolates the first transmitter from the second communication circuit element and isolates the second transmitter from the first communication circuit element.

10. The memory device of claim 6 wherein the configurable grouping mechanism includes a set of switches for routing the first signal and the second signal between the first transmitter, the second transmitter, the first communication circuit element, the second communication circuit element, or a combination thereof.

11. The memory device of claim 10 wherein the configurable grouping mechanism includes the set of switches according to an H-bridge configuration.

12. The memory device of claim 1 further comprising:
a first receiver coupled to the first communication circuit element and the configurable grouping mechanism, the first receiver configured to receive the first signal; and
a second receiver coupled to the second communication circuit element and the configurable grouping mechanism, the second receiver configured to receive the second signal.

13. The memory device of claim 12 wherein:
the first receiver includes a first reference portion configured to provide a first reference level for detecting levels of the first signal using the first receiver;
the second receiver includes a second reference portion configured to provide a second reference level for detecting levels of the second signal using the second receiver; and
the configurable grouping mechanism is configured to electrically couple the first signal to the second reference portion and couple the second signal to the first reference portion for operating the first communication circuit element and the second communication circuit element as a group.

14. The memory device of claim 12 wherein the configurable grouping mechanism is configured to isolate the first receiver and the second receiver to independently operate the first communication circuit element and the second communication circuit element, wherein the configurable grouping mechanism isolates the first receiver from the second signal and isolates the second receiver from the first signal.

15. The memory device of claim 1 wherein the first communication circuit element and the second communication circuit element are both configured to implement bidirectional communication between a memory array and a controller of the memory device.

16. A memory device, comprising:
a memory array including a first memory circuit element and a second memory circuit element, each for sending or receiving signals; and
a controller coupled to the memory array, the controller including a first controller circuit element and a second controller circuit element, wherein the first controller circuit element is electrically coupled to the first memory circuit element and the second controller circuit element is electrically coupled to the second memory circuit element;
wherein the memory array and the controller include a configurable grouping mechanism coupled to the first memory circuit element, the second memory circuit element, the first controller circuit element, and the second controller circuit element, the configurable grouping mechanism configured to select between:
operating the first memory circuit element and the first controller circuit element independent from the second memory circuit element and the second controller circuit element for an independent communication mode, and
operating the first memory circuit element and the first controller circuit element in correlation with the second memory circuit element and the second controller circuit element for a grouped communication mode.

17. The memory device of claim 16 wherein the configurable grouping mechanism is configured to implement the grouped communication mode based on communicating a data stream using the first memory circuit element, the first controller circuit element, the second memory circuit element, and the second controller circuit element.

18. The memory device of claim 17 wherein the configurable grouping mechanism is configured to implement the grouped communication mode based on communicating the data stream using a first signal with a second signal that is complementary to the first signal, wherein the first signal is communicated between the first memory circuit element and the first controller circuit element and the second signal is communicated between the second memory circuit element and the second controller circuit element.

19. The memory device of claim 18 wherein the configurable grouping mechanism is configured to implement the grouped communication mode based on communicati

Assignees

• Micron Technology Inc

Inventors

• Rowley Matthew D
• Bauer Mark

Classifications

• G06F13/1668 Primary

  Details of memory controller · CPC title

• H04L67/2885 Primary

  Hierarchically arranged intermediate devices, e.g. for hierarchical caching · CPC title

• H04L69/18

  Multiprotocol handlers, e.g. single devices capable of handling multiple protocols · CPC title

• H04W88/16

  Gateway arrangements · CPC title

• H04W88/06

  adapted for operation in multiple networks {or having at least two operational modes}, e.g. multi-mode terminals · CPC title