Stacked semiconductor package having mold vias and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-10418353-B2
Application number	US-201715715449-A
Country	US
Kind code	B2
Filing date	Sep 26, 2017
Priority date	May 11, 2017
Publication date	Sep 17, 2019
Grant date	Sep 17, 2019

Abstract

A stacked semiconductor package includes a first semiconductor chip having a first active surface over which first bonding pads including peripheral bonding pads and central bonding pads are arranged, a first encapsulation member, two second semiconductor chips having second active surfaces over which second bonding pads are arranged at one side peripheries and disposed to be separated from each other such that the second active surfaces face the first active surface and the second bonding pads overlap with the peripheral bonding pads, first coupling members interposed between the peripheral bonding pads and the second bonding pads, a second encapsulation member formed over second side surfaces of the second semiconductor chips including a region between the second semiconductor chips, and a mold via formed through a portion of the second encapsulation member in the region between the second semiconductor chips and coupled with the central bonding pads.

First claim

What is claimed is:

1. A stacked semiconductor package comprising:
a first semiconductor chip having a first active surface over which first bonding pads including peripheral bonding pads and central bonding pad are arranged;
a first encapsulation member formed over at least first side surfaces of the first semiconductor chip;
two second semiconductor chips having second active surfaces over which second bonding pads are arranged at side peripheries adjacent to the first semiconductor chip, and disposed to be separated from each other such that the second active surfaces face the first active surface and the second bonding pads overlap with the peripheral bonding pads;
first coupling members interposed between the peripheral bonding pads of the first semiconductor chip and the second bonding pads of the second semiconductor chips;
a second encapsulation member formed over second side surfaces of the second semiconductor chips including a region between the second semiconductor chips; and
a mold via formed through a portion of the second encapsulation member in the region between the second semiconductor chips and directly coupled with the central bonding pad of the first semiconductor chip,
wherein the first encapsulation member has a first front surface which is coplanar with the first active surface of the first semiconductor chip and a first back surface which is coplanar with a first surface of the first semiconductor chip facing away from the first active surface, and
wherein the second encapsulation member has a second front surface which is in contact with the first encapsulation member and a second back surface which is coplanar with second surfaces of the second semiconductor chips facing away from the second active surfaces.

2. The stacked semiconductor package according to claim 1 , wherein the first semiconductor chip comprises a logic chip, and the second semiconductor chips comprise memory chips.

3. The stacked semiconductor package according to claim 1 , wherein the second encapsulation member is formed to be in contact with the first semiconductor chip and the first encapsulation member.

4. The stacked semiconductor package according to claim 1 , further comprising:
bump pad formed under the mold via which are disposed at the second back surface of the second encapsulation member;
dummy pads formed under the second surfaces of the second semiconductor chips;
second coupling member formed under the bump pad; and
support members formed under the dummy pads.

5. The stacked semiconductor package according to claim 4 , further comprising:
a substrate disposed to face the second surfaces of the second semiconductor chips and the second back surface of the second encapsulation member, and having a top surface over which bond finger to be electrically coupled with the second coupling member is arranged and a bottom surface under which electrode terminal to be electrically coupled with the bond finger is arranged.

6. The stacked semiconductor package according to claim 5 , further comprising:
a third encapsulation member formed over the top surface of the substrate to cover side surfaces of the first and second encapsulation members and fill spaces between the second semiconductor chips and the second encapsulation member and the top surface of the substrate; and
external coupling member formed under the electrode terminal.

7. The stacked semiconductor package according to claim 5 , further comprising:
an underfill formed to fill spaces between the second surfaces of the second semiconductor chips and the second back surface of the second encapsulation member and the top surface of the substrate; and
external coupling member formed under the electrode terminal.

8. The stacked semiconductor package according to claim 1 , further comprising:
a redistribution layer formed under the second surfaces of the second semiconductor chips, the second back surface of the second encapsulation member, and the mold via.

9. The stacked semiconductor package according to claim 8 , wherein the redistribution layer comprises:
a first dielectric layer formed under the second surfaces of the second semiconductor chips, the second back surface of the second encapsulation member, and the mold via in such a way as to leave exposed the mold via;
redistribution line formed under the first dielectric layer such that one end of the redistribution line is coupled with the mold via which is exposed;
a second dielectric layer formed under the first dielectric layer in such a way as to cover the redistribution line except the other end of the redistribution line facing away from the one end; and
redistribution pad formed under the second dielectric layer in such a way as to be coupled with the other end of the redistribution line which is exposed.

10. The stacked semiconductor package according to claim 9 , further comprising:
external coupling member formed under the redistribution pad.

Assignees

• Sk Hynix Inc

Inventors

• Lee Sang-Eun
• Lee Hyung-Dong
• Ko Eun

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W70/099

  Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers · CPC title

• H10W72/853

  On the same surface · CPC title

• H10W72/9413

  on encapsulations · CPC title