Air gap spacer formation for nano-scale semiconductor devices

Patent metadata

Field	Value
Publication number	US-10418277-B2
Application number	US-201815977437-A
Country	US
Kind code	B2
Filing date	May 11, 2018
Priority date	Aug 9, 2016
Publication date	Sep 17, 2019
Grant date	Sep 17, 2019

Abstract

Semiconductor devices having air gap spacers that are formed as part of BEOL or MOL layers of the semiconductor devices are provided, as well as methods for fabricating such air gap spacers. For example, a method comprises forming a first metallic structure and a second metallic structure on a substrate, wherein the first and second metallic structures are disposed adjacent to each other with insulating material disposed between the first and second metallic structures. The insulating material is etched to form a space between the first and second metallic structures. A layer of dielectric material is deposited over the first and second metallic structures using a pinch-off deposition process to form an air gap in the space between the first and second metallic structures, wherein a portion of the air gap extends above an upper surface of at least one of the first metallic structure and the second metallic structure.

First claim

We claim:

1. A method, comprising:
forming a first metallic structure and a second metallic structure on a substrate, wherein the first and second metallic structures are disposed adjacent to each other with insulating material disposed between the first and second metallic structures;
etching the insulating material to form a space between the first and second metallic structures; and
depositing a layer of dielectric material over the first and second metallic structures to form an air gap in the space between the first and second metallic structures;
wherein a portion of the air gap extends above an upper surface of at least one of the first metallic structure and the second metallic structure;
wherein depositing the layer of dielectric material over the first and second metallic structures comprises:
depositing a non-conformal layer of dielectric material to form a dielectric capping layer having a pinch-off region that is aligned to the space between the first and second metallic structures;
wherein the pinch-off region is formed in the dielectric capping layer above the upper surface of the at least one first metallic structure and second metallic structure; and

wherein depositing the layer of dielectric material comprises depositing a non-conformal layer of silicon carbon nitride material using a plasma-enhanced chemical vapor deposition process, wherein parameters of the plasma-enhanced chemical vapor deposition process comprise (i) a gas environment comprising trimethyl silane at a flow rate in a range of 200-500 standard cubic centimeter per minute and ammonia at a flow rate in a range of 300-800 standard cubic centimeter per minute, (ii) RF power in a range of 300-600 watts, (iii) pressure in a range of 2-6 Torr, and (iv) a deposition rate in a range of 0.5-5 nanometers/second.

2. The method of claim 1 , wherein the first metallic structure comprises a first metal line formed in an ILD (interlevel dielectric) layer of a BEOL (back-end-of-line) interconnect structure, and wherein the second metallic structure comprises a second metal line formed in the ILD layer of the BEOL interconnect structure.

3. The method of claim 2 , wherein the portion of the air gap extends above the first metal line and above the second metal line.

4. The method of claim 1 , wherein the first metallic structure comprises a device contact, and wherein the second metallic structure comprises a gate structure of a transistor.

5. The method of claim 4 , wherein the device contact is taller than the gate structure, and wherein the portion of the air gap extends above the gate structure and below an upper surface of the device contact.

6. The method of claim 1 , wherein depositing the non-conformal layer of dielectric material comprise setting the parameters of the plasma-enhanced chemical vapor deposition process to obtain a level of conformality of about 40% or less.

7. The method of claim 1 , further comprising forming a conformal liner layer within the space between the first and second metallic structures before depositing the layer of dielectric material over the first and second metallic structures to form the air gap in the space between the first and second metallic structures.

8. The method of claim 7 , wherein forming the conformal liner layer comprises depositing a plurality of conformal dielectric layers to thereby form a multi-layer liner.

9. The method of claim 7 , wherein the conformal liner layer is formed of a dielectric material comprising one or more of SiN, SiCN, SiNO, SiCNO, SiBN, SiCBN, and SiC.

10. The method of claim 7 , wherein the conformal liner layer comprises a thickness in a range of about 0.5 nm to about 5 nm.

11. The method of claim 1 , wherein the air gap extends past an end of at least one of the first and second metallic structures.

12. A method, comprising:
forming a fin field-effect transistor device on a substrate, the fin field-effect transistor device comprising a vertical semiconductor fin, a metallic gate structure formed over a portion of the vertical semiconductor fin, a gate encapsulation layer covering upper and sidewall surfaces of the metallic gate structure, and first and second source/drain contacts formed in contact with portions of the vertical semiconductor fin extending from the sidewall surfaces of the metallic gate structure, wherein gate encapsulation layer comprises gate sidewall spacers disposed between the metallic gate structure and the first and second source/drain contacts and a gate capping layer disposed over the upper surface of the metallic gate structure;
etching the gate encapsulation layer to form spaces between the metallic gate structure and the first and second source/drain contacts; and
depositing a layer of dielectric material over the fin field-effect transistor device to thereby cover the upper surface of the metallic gate structure with the dielectric material and form air gaps in the spaces between the metallic gate structure and the first and second source/drain contacts;
wherein upper portions of the air gaps are disposed above the upper surface of the metallic gate structure and disposed below upper surfaces of the first and second source/drain contacts; and
wherein bottom portions of the air gaps are disposed below bottom surfaces of the first and second source/drain contacts.

13. The method of claim 12 , wherein depositing the layer of dielectric material over the fin field-effect transistor device comprises depositing a non-conformal layer of dielectric material to form a dielectric capping layer which is disposed on the upper surface of the metallic gate structure and which comprises pinch-off regions that are aligned to the spaces between the metallic gate structure and the first and second source/drain contacts.

14. The method of claim 13 , wherein depositing the layer of dielectric material comprises depositing a non-conformal layer of silicon nitride material using a plasma-enhanced chemical vapor deposition process, wherein parameters of the plasma-enhanced chemical vapor deposition process comprise (i) a gas environment comprising silane at a flow rate in a range of 100-500 standard cubic centimeter per minute and ammonia at a flow rate in a range of 200-1000 standard cubic centimeter per minute, (ii) RF power in a range of 200-600 watts, (iii) pressure in a range of 1-8 Torr, and (iv) a deposition rate in a range of 0.5-8 nanometers/second.

15. The method 14 , wherein depositing the non-conformal layer of dielectric material comprise setting the parameters of the plasma-enhanced chemical vapor deposition process to obtain a level of conformality of about 40% or less.

16. The method of claim 12 , wherein the layer of dielectric material comprises a low-k dielectric material having a dielectric constant that is about 5.0 or less.

17. The method of claim 12 , wherein the layer of dielectric material comprises at least one of SiCOH, porous p-SiCOH, SiCN, SiNO, carbon-rich SiCNH, SiC, p-SiCNH, and SiN.

18. The method of claim 12 , further comprising forming a conformal liner layer over the first and second source/drain contacts and the metallic gate structure to line the sidewall surfaces in the spaces between the metallic gate structure and the first and second source/drain contacts, before depositing the layer of dielectric material form the air gaps in the spaces between the metallic gate structure and the first and second source/drain contacts.

19. The method of claim 18 , wherein the spaces between the metallic gate structure and the first and second source/drain c

Assignees

• IBM

Inventors

• Cheng Kangguo
• Haigh Thomas J
• Li Juntao
• Liniger Eric G
• Mehta Sanjay C
• Nguyen Son V
• Park Chanro
• Yamashita Tenko

Classifications

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/6922

  the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC · CPC title

• H10P14/6905

  being a silicon carbide or silicon carbonitride and not containing oxygen, e.g. SiC or SiC:H · CPC title

• H10P14/6336

  in the presence of a plasma [PECVD] · CPC title

• H10W20/48 Primary

  Insulating materials thereof · CPC title