Method for semiconductor device structure
US-12154970-B2 · Nov 26, 2024 · US
Semiconductor devices and method of manufacturing the same
US8952452B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8952452-B2 |
| Application number | US-201213692012-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 3, 2012 |
| Priority date | Mar 20, 2012 |
| Publication date | Feb 10, 2015 |
| Grant date | Feb 10, 2015 |
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Abstract
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Semiconductor devices, and a method of manufacturing the same, include a gate insulating film pattern over a semiconductor substrate. A gate electrode is formed over the gate insulating film pattern. A spacer structure is formed on at least one side of the gate electrode and the gate insulating film pattern. The spacer structure includes a first insulating film spacer contacting the gate insulating film pattern, and a second insulating film spacer on an outer side of the first insulating film spacer. The semiconductor device has an air gap between the first insulating film spacer and the second insulating film spacer.
First claim
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What is claimed is: 1. A semiconductor device, comprising: a gate insulating film pattern over a semiconductor substrate; a gate electrode over the gate insulating film pattern; a spacer structure on at least one side of the gate electrode and the gate insulating film pattern, the spacer structure including, a first insulating film spacer contacting the gate insulating film pattern; and a second insulating film spacer on an outer side of the first insulating film spacer,…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US8952452B2 cover?
- Semiconductor devices, and a method of manufacturing the same, include a gate insulating film pattern over a semiconductor substrate. A gate electrode is formed over the gate insulating film pattern. A spacer structure is formed on at least one side of the gate electrode and the gate insulating film pattern. The spacer structure includes a first insulating film spacer contacting the gate insula…
- Who is the assignee on this patent?
- Samsung Electronics Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification H10D64/021. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Feb 10 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).