Write-through detection for a memory circuit with an analog bypass portion

Patent metadata

Field	Value
Publication number	US-10417136-B2
Application number	US-201715851264-A
Country	US
Kind code	B2
Filing date	Dec 21, 2017
Priority date	Dec 21, 2017
Publication date	Sep 17, 2019
Grant date	Sep 17, 2019

Abstract

The circuit includes a memory array arranged as rows and columns of memory cells. An array portion stores a respective memory word in a given one of the rows in response to a word-write signal corresponding to a write address of the given one of the rows and in response to a plurality of bit-write signals associated with the plurality of columns, and reads a respective memory word from a given one of the rows in response to a word-read signal corresponding to a read address of the given one of the rows and in response to a plurality of bit-read signals associated with the plurality of columns. The circuit also includes a write-through detection system that activates an analog bypass portion to read the memory word from the analog bypass portion in response to the read address being the same as the write address.

First claim

What is claimed is:

1. A memory circuit comprising:
a memory array comprising an array portion and an analog bypass portion, the array portion comprising rows and columns of memory cells, the array portion stores a respective memory word in a given one of the rows in response to a word-write signal corresponding to a write address of the given one of the rows and in response to a plurality of bit-write signals associated with the plurality of columns, and to read a respective memory word from the given one of the rows or from another one of the rows in response to a word-read signal corresponding to a read address of the given one or the other one of the rows and in response to a plurality of bit-read signals associated with the plurality of columns; and
a write-through detection system that activates the analog bypass portion to read the memory word from the analog bypass portion in response to the read address being the same as the write address.

2. The circuit of claim 1 , wherein the array portion stores the respective memory word during a write operation and reads the respective memory word during a read operation, wherein the write-through detection system activates the analog bypass portion to read the plurality of bit-write signals corresponding to the memory word in response to the read address being the same as the write address during the write operation.

3. The circuit of claim 1 , further comprising a row peripheral circuit that receives a write address signal corresponding to the write address of the given one of the rows and generates the word-write signal to activate the given one of the rows to write the memory word during a write operation, the row peripheral circuit also receiving a read address signal corresponding to the read address of the given one or the other one of the rows and generates the word-read signal to activate the given one or the other one of the rows to read the memory word during a read operation.

4. The circuit of claim 3 , wherein the write-through detection system is to compare the write address signal and the read address signal and to activate the analog bypass portion to read the plurality of bit-write signals corresponding to the memory word in response to the write address signal addressing the same memory row as the read address signal during the write operation.

5. The circuit of claim 1 , wherein the write-through detection system receives a read-enable signal during a read operation, wherein the memory array reads the memory word from the given one of the rows or the analog bypass portion in response to the word-read signal and the read-enable signal.

6. The circuit of claim 5 , further comprising a read address decoder that generates the word-read signal to select the given one of the rows to read the memory word from the given one of the rows, wherein the write-through detection system comprises logic to deactivate the read address decoder and to activate the analog bypass portion in response to the read-enable signal and in response to the read address being the same as the write address.

7. The circuit of claim 6 , wherein the write-through detection system comprises a comparator that compares the write address and the read address and to generate a control signal in response to the write address being the same as the read address, wherein the logic deactivates the read address decoder and to activate the analog bypass portion in response to the read-enable signal and the control signal.

8. The circuit of claim 7 , wherein the logic comprises:
a first AND-gate that receives the read-enable signal and an inverted state of the control signal and generates an array-enable signal to activate and deactivate the read address decoder; and
a second AND-gate that receives the read-enable signal and the control signal and generates a write-through signal to activate and deactivate the analog bypass portion.

9. The circuit of claim 1 , wherein the analog bypass portion comprises a row of cells coupled to the memory array, each of the cells of the analog bypass portion being arranged to provide an output bit corresponding to a respective one of the plurality of bit-read signals in response to activation of the analog bypass portion via a write-through signal.

10. The circuit of claim 9 , wherein each of the cells of the analog bypass portion comprises:
a superconducting quantum interference device (SQUID) that provides an output signal having a logic-state corresponding to a logic-state associated with the respective one of the plurality of bit-write signals;
a first transformer coupled to the SQUID to inductively couple the write-through signal to the SQUID as a bias; and
a second transformer coupled to the SQUID to inductively couple the respective one of the plurality of bit-write signals to the SQUID, such that the SQUID provides the output signal in response to the write-through signal and the respective one of the plurality of bit-write signals.

11. The circuit of claim 1 , wherein each of the memory cells of the memory array comprises a superconducting hysteretic memory element to store an associated logic state in response to the word-write signal and a respective one of the plurality of bit-write signals.

12. The circuit of claim 1 , wherein the plurality of bit-read signals propagate on a respective plurality of bit-read lines that extend through each of the rows of the array portion of the memory array and through the analog bypass portion of the memory array, the system further comprising a sense amplifier coupled to the plurality of bit-read lines to read the memory word.

13. A method for reading data from a memory array during a write operation, the memory array comprising rows and columns of memory cells, the method comprising:
providing a write address signal corresponding to a write address of given one of the rows;
providing a word-write signal associated with the write address via a write address decoder to activate the given one of the rows during a write operation;
providing a plurality of bit-write signals associated with respective columns of the memory array to store a memory word in the given one of the rows during the write operation;
providing a read address signal corresponding to a read address of the given one of the rows or another one of the rows during the write operation;
comparing the read address signal and the write address signal;
activating an analog bypass portion of the memory array in response to the read address signal being the same as the write address signal; and
reading the memory word from the analog bypass portion of the memory array in response to activation of the analog bypass portion.

14. The method of claim 13 , wherein reading the memory word comprises:
generating a write-through signal in response to the read address signal addressing the same memory row as the write address signal; and
reading the plurality of bit-write signals from the analog bypass portion of the memory array.

15. The method of claim 13 , further comprising providing a read-enable signal during the write operation, wherein comparing the read address signal and the write address signal comprises generating a control signal to indicate that the read address signal is the same as the write address signal, wherein activating the analog bypass portion comprises:
deactivating a read address decoder in response to the control signal and the read-enable signal, wherein the read address decoder generates a word-read signal to select a given one of the rows to read a respective memory word from the given one of the rows during a read operation; and
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Assignees

• Horner Jeremy William
• Herr Quentin P
• Northrop Grumman Systems Corp

Inventors

• Horner Jeremy William
• Herr Quentin P

Classifications

• G11C8/08

  Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines · CPC title

• G06F15/8038

  Associative processors · CPC title

• G11C7/18

  Bit line organisation; Bit line lay-out · CPC title

• G11C2207/2209

  Concurrent read and write · CPC title

• G06F12/0207

  with multidimensional access, e.g. row/column, matrix · CPC title