Timing control in a quantum memory system

Patent metadata

Field	Value
Publication number	US-9761305-B2
Application number	US-201615170616-A
Country	US
Kind code	B2
Filing date	Jun 1, 2016
Priority date	Mar 5, 2015
Publication date	Sep 12, 2017
Grant date	Sep 12, 2017

Abstract

One embodiment describes a quantum memory system. The system includes an array controller that comprises a plurality of flux pumps configured to provide write currents in a write operation and read currents in a read operation with respect to a plurality of quantum memory cells, the array controller being configured to control timing associated with the write operation and the read operation in response to memory request signals based on application of the write currents and the read currents and based on recharging flux associated with the plurality of flux pumps.

First claim

What is claimed is:

1. A memory system comprising an array controller, the array controller comprising a plurality of flux pumps configured to provide at least one write current in a write operation and at least one read current in a read operation with respect to a plurality of memory cells arranged in an array of at least one row and at least one column, the array controller being configured to control timing associated with the write operation and the read operation in response to memory request signals based on application of the at least one write current and the at least one read current and based on recharging flux associated with the plurality of flux pumps.

2. The system of claim 1 , wherein the array controller comprises a timing controller configured to generate a busy signal in response to a given one of the memory request signals based on application of conflicting write currents or conflicting read currents or based on insufficient flux of a respective one or more of the plurality of flux pumps associated with the selected row or the columns of the array of the at least one row and the at least one column, the busy signal comprising one of a first state to allow a respective one of the write operation and the read operation and a second state to prohibit the respective one of the write operation and the read operation.

3. The system of claim 2 , wherein the array controller further comprises an address controller configured to receive the memory request signals and to generate address signals to control the plurality of flux pumps to provide the write currents to write the binary logic state to a selected row of the array of the at least one row and the at least one column or to provide the read currents to read the binary logic state from a selected row of the array of the at least one row and the at least one column.

4. The system of claim 3 , wherein the timing controller comprises:
a busy address register configured to store an address associated with the selected row of the array of the at least one row and the at least one column corresponding to a previously selected row of the array of the at least one row and the at least one column; and
a comparator configured to generate the busy signal based on a comparison of one of a time and an address associated with a subsequent selected row of the array of the at least one row and the at least one column based on the memory request signals with a respective one of a time associated with the previously selected row and the addresses associated with the previously selected row.

5. The system of claim 4 , wherein the timing controller further comprises:
a timer to generate a real-time timing signal; and
a plurality of registers to control access to word flux pumps and bit flux pumps of the plurality of flux pumps associated with the array, each of the registers being configured to store a predetermined time corresponding to the control of the one or more of the plurality of flux pumps.

6. The system of claim 5 , wherein the plurality of registers comprises:
a busy duration register to provide a register value that corresponds to a predetermined time duration associated with previously asserted bit-write or bit-read currents and word-write or word-read currents associated with the bit flux pumps and the word flux pumps of the previously selected row and a previously selected column of the array of the at least one row and the at least one column;
a bit-line assertion offset register to provide a register value that corresponds to a predetermined time duration associated with asserting the previously asserted bit-write or bit-read currents associated with the bit flux pumps associated with the previously selected column of the array;
a bit-line de-assertion offset register to provide a register value that corresponds to a predetermined time-value duration associated with de-asserting the previously asserted bit-write or bit-read currents associated with the bit flux pumps of the previously selected column;
a word-line assertion register to provide a register value that corresponds to a predetermined time duration associated with asserting the previously asserted word-write or word-read currents associated with the word flux pumps of the previously selected row; and
a word-line de-assertion register to provide a register value that corresponds to a predetermined time value duration associated with de-asserting the previously asserted word-write or word-read currents associated with the word flux pumps of the previously selected row.

7. The system of claim 6 , wherein the timing controller further comprises a plurality of adders to receive a respective register value that corresponds to a given predetermined time value from the plurality of registers and to add the real-time timing signal to generate a plurality of predetermined time offset values, the plurality of predetermined time offset values being employed by the timing controller to control access to the bit flux pumps and the word flux pumps of the plurality of flux pumps.

8. The system of claim 7 , wherein the timing controller further comprises:
an event sequencer to receive the plurality of predetermined time offset values, the memory request signals and the real-time timing signal to control the access to the bit flux pumps and word flux pumps, wherein the plurality of predetermined time offset values define thresholds for generating the busy signal corresponding to a bit-line busy signal, bit-line timing signals that are configured to control the bit flux pumps, and word-line timing signals that are configured to control the word flux pumps.

9. The system of claim 8 , wherein the event sequencer comprises:
a busy timing controller to generate the bit-line busy signal based on the memory request signals, the real-time timing signal and a given predetermined time offset value to indicate that the previously selected row is one of available and prohibited for access for a subsequent read operation or write operation.

10. The system of claim 8 , wherein the event sequencer further comprises:
a bit-line timing controller to generate the bit-line timing signals based on the memory request signals, the real-time timing signal and one of a first predetermined time offset value and a second predetermined time offset value associated with one of the bit-line assertion register and the bit-line de-assertion register, respectively, to control one of the asserting and the de-asserting of the previously asserted bit-write or bit-read currents associated with the bit flux pumps of the previously selected column; and
a word-line timing controller to generate the word-line timing signals based on the memory request signals, the real-time timing signal and one of a first predetermined time offset value and a second predetermined time offset value associated with one of the word-line assertion register and the word-line de-assertion register to control one of the asserting and the de-asserting the previously asserted word-write or word-read currents associated with the word flux pumps associated with the previously selected row.

11. The system of claim 2 , wherein the array controller comprise a plurality of timing controllers configured to generate a plurality of busy signals in response to the memory request signals to provide simultaneous busy-state tracking of the plurality of memory cells.

12. The system of claim 1 , wherein the plurality of memory cells are a plurality of quantum memory cells.

13. The system of claim 1 , wherein the array of rows and columns comprises an array of rows and a plurality of sets of columns, the plurality of sets of col

Assignees

• Reohr William Robert
• Shauck Steven Brian
• Miller Donald Lynn
• Horner Jeremy William
• Josephsen Nathan Trent
• Northrop Grumman Systems Corp

Inventors

• Reohr William Robert
• Shauck Steven Brian
• Miller Donald Lynn
• Horner Jeremy William
• Josephsen Nathan Trent

Classifications

• G11C19/32

  using super-conductive elements · CPC title

• G11C11/1693

  Timing circuits or methods · CPC title

• G11C11/1659

  Cell access · CPC title

• G11C11/1657

  Word-line or row circuits · CPC title

• G11C11/1655

  Bit-line or column circuits · CPC title